Browsing by Author "He, Wen-Quan"

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Dynamic Error-Compensated Fixed-Width Booth Multiplier Based on Conditional-Probability of Input Series
(2016-08)
He, Wen-Quan
;
Chen, Yuan-Ho
;
Jou, Shyh-Jye
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper proposes a dynamic error-compensated circuit for a fixed-width Booth multiplier based on the conditional probability of input series (CPIS), which enables high-speed operation and low circuit overhead. The dynamic compensated value is produced directly from the multiplier of input series simultaneously with the Booth encoder and therefore does not affect the critical path. The compensated formula is derived using a mathematical probability model, rather than time-consuming simulation. This formula is a function of bit-length of the multiplier; thus, the compensated circuit is easily implemented for bit-length of 32, 64, or longer. Accuracy-efficiency, which indicates the signal-to-noise ratio per unit area and unit delay, is included for ease of comparison. Compared with previous works, the greatest advantage of the proposed CPIS is high speed. Furthermore, the proposed CPIS achieves higher accuracy-efficiency. Implemented using the TSMC 0.18-m CMOS process, the proposed 32-bit Booth multiplier has an operation frequency of 50 MHz with power consumption of 7.3 mW.
Full-Digital High Throughput Design of Adaptive Decision Feedback Equalizers Using Coefficient-Lookahead
(2015-01-01)
He, Wen-Quan
;
Lin, Yu-Chun
;
Hung, Jui-Yi
;
Jou, Shyh-Jye
;
電子工程學系及電子研究所
This paper proposes a novel full-digital architecture of adaptive decision feedback equalizer (ADFE) for wireline 2-level pulse amplitude modulation (2-PAM) systems. It is well known that the feedback loop in DFE limits the greatest achievable speed. The proposed scheme begins by deriving coefficient-lookahead concept based on a reasonable assumption, whereupon a preliminary architecture can be implemented using the formula derived. Furthermore, according to channel characteristics, the formula derived can be simplified to break the feedback loop. Finally, the architecture can be easily pipelined and processed in parallel to achieve high throughput rate. Thus, the proposed design is a high speed design with parallel and pipeline architecture. This paper used a TSMC 40 nm CMOS process to fabricate the proposed design with a build-in self-test (BIST) circuit. The measured results show that the throughput rate is up to 16 Gbps.
High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation
(2015-08-01)
He, Wen-Quan
;
Chen, Yuan-Ho
;
Jou, Shyh-Jye
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This study developed a high accuracy dynamic error-compensation circuit for fixed-width Booth multipliers based on probability and computer simulation (PACS). PACS begins by generating several potential solutions based on both conditional and expected probability, whereupon the accuracy of the solutions is verified using computer simulation and the solution with the highest accuracy is selected. In addition to being highly accurate, the proposed PACS approach is area-effective. This study used the TSMC 0.18-mu m CMOS to fabricate a 16-bit Booth multiplier with an operating frequency of 100 MHz and power consumption of 6.7 mW.