Browsing by Author "Ho, Chen-Kang"

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10GSamples/s, 4-bit, 1.2V, design-for-testability ADC and DAC in 0.13 mu m CMOS technology
(2007)
Liang, Sheng-Chuan
;
Huang, Ding-Jyun
;
Ho, Chen-Kang
;
Hong, Hao-Chiao
;
電控工程研究所
This paper demonstrates a 10GS/s, 4-bit, flash analog-to-digital converter (ADC) and current-steering digital-to-analog converter (DAC) pair for the design or advanced serial-link transceivers. Current mode logic (CML) gates are used to alleviate the severe power bouncing. The active feedback amplifiers, CML, and wave-pipelining technique help achieve the ultimate 10 GHz sampling rate. A design-for-testability circuit using the digital loop-back scheme is added to address the difficulty of at-speed measurements. The experimental results show that the cascaded ADC and DAC pair achieves a 27.3 dBc spurious-free dynamic range and a 25.0 dB signal-to-noise ratio with the 1.11 GHz, -1 dBm stimulus. It corresponds to an ENOB of 3.86 bits. The test chip totally consumes 420 mW from a 1.2V supply. The areas of the ADC and DAC are 0.1575 mm(2) and 0.0636 mm(2), respectively in 0.13 mu m CMOS technology.
A 6-GS/s, 6-bit, At-speed Testable ADC and DAC Pair in 0.13 mu m CMOS
(2009)
Ho, Chen-Kang
;
Hong, Hao-Chiao
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper demonstrates a 6-GS/s 6-bit flash ADC and current-steering DAC pair in 0.13 mu m CMOS. Averaging and interpolating techniques are applied to reduce the offsets and to save the power of the ADC. Current mode logics are used to achieve a high speed and to overcome the severe power bouncing issue. Design-for-testability circuits are added to conduct the at-speed tests by internally cascading the ADC and DAC. The cascaded ADC and DAC pair clocked at 6GHz achieves a 37.0 dB signal-to-noise ratio and a 26.0 dBc spurious-free dynamic range with the -1 dBFS, 502 MHz stimulus. The ADC and DAC consumes 655 mW and 115 mW from a 1.2-V supply, respectively.