Browsing by Author "Ho, Chia-Hua"

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3D resistive RAM cell design for high-density storage class memory-a review
(2016-06)
Hudec, Boris
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Hsu, Chung-Wei
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Wang, I-Ting
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Lai, Wei-Li
;
Chang, Che-Chia
In this article, we comprehensively review recent progress in the ReRAM cell technology for 3D integration focusing on a material/device level. First we briefly mention pioneering work on high-density crossbar ReRAM arrays which paved the way to 3D integration. We discuss the two main proposed 3D integration schemes-3D horizontally stacked ReRAM vs 3D Vertical ReRAM and their respective advantages and disadvantages. We follow with the detailed memory cell design on important work in both areas, utilizing either filamentary or interface-limited switching mechanisms. We also discuss our own contributions on HfO2-based filamentary 3D Vertical ReRAM as well as TaOx/TiO2 bilayer-based self-rectifying 3D Vertical ReRAM. Finally, we summarize the present status and provide an outlook for the nearterm future.
A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications
(2012-04-01)
Chen, Min-Cheng
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Chen, Hao-Yu
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Lin, Chia-Yi
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Chien, Chao-Hsin
;
Hsieh, Tsung-Fan
This paper reports a versatile nano-sensor technology using "top-down" poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH) and sensitive deoxyribonucleic acid (DNA) detection ability (100 pM) at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically Vth-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady Vth adjustment window (>2 V Programming/Erasing window). The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording.
Effect of oxygen concentration on characteristics of NiOx-based resistance random access memory
(2007-02-01)
Lee, Ming-Daou
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Ho, Chia-Hua
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Lo, Chi-Kuen
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Peng, Tai-Yen
;
Yao, Yeong-Der
The resistance bistability and the switching effect has been systematically studied in nickel oxide films with variable oxygen concentrations. Both the switching bias voltage and the resistance ratio of RESET to SET were found to be strongly concentration dependent. Meanwhile, the electrical characteristics can be exactly examined by an Schottky emission. By means of mathematical fitting, the resistance bistability seems to be related to the alternating of dielectric constant and the barrier height. Furthermore, the room temperature cycle endurance with a distinguishable operation window was found to exceed 800. This indicates that the nickel oxide has the potential to be a promising material on resistance random access memory.
Effects of Bonding Technology and Thinning Process in Three-Dimensional Integration on Device Characteristics
(2012-10-01)
Lu, Cheng-Hsien
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Cheng, Chuan-An
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Ho, Chia-Hua
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Chen, Kuan-Neng
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電子工程學系及電子研究所
This research is to investigate the effects of bonding technology and thinning process on the electrical properties of 0.35 mu m technology node n-MOSFET devices. After the bonding process, by changing the bonding temperature up to 400 degrees C and bonding force up to 2.5 x 10(5) Pa, these devices still have the same electrical performances. In addition, thinning process was applied to investigate the stress which would affect the electrical properties of n-MOSFETs. The electrical performances of devices do not change for substrate thickness larger than 466 mu m.
Enhanced Properties in Conductive-Bridge Resistive Switching Memory With Oxide-Nitride Bilayer Structure
(2016-10)
Tsai, Tsung-Ling
;
Jiang, Fa-Shen
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Ho, Chia-Hua
;
Lin, Chen-Hsi
;
Tseng, Tseung-Yuen
In this letter, we propose a new method to improve resistive switching properties in ZrO2-based conductive-bridge resistive memory devices by introducing a thin AlN layer with high thermal conductivity between the ZrO2 layer and TiN bottom electrode. Compared with the Cu/TiW/ZrO2/TiN single-layer device, the Cu/TiW/ZrO2/AlN/TiN bilayer device exhibits lower operation voltages, higher endurance performance, and higher resistive switching uniformity. These substantial improvements in the resistive switching properties are attributed to the formation and rupture of conductive filament that can be effectively controlled in the device after inserting the AlN layer.
Investigation of thermal stability and reliability of HfO2 based resistive random access memory devices with cross-bar structure
(2015-05-14)
Chand, Umesh
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Huang, Kuan-Chang
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Huang, Chun-Yang
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Ho, Chia-Hua
;
Lin, Chen-Hsi
The effect of the annealing treatment of a HfO2 resistive switching layer and the memory performance of a HfO2-based resistive random access memory (cross-bar structure) device were investigated. Oxygen is released from HfO2 resistive switching layers during vacuum annealing, leading to unstable resistive switching properties. This oxygen release problem can be suppressed by inserting an Al2O3 thin film, which has a lower Gibbs free energy, between the HfO2 layer and top electrode to form a Ti/Al2O3/HfO2/TiN structure. This device structure exhibited good reliability after high temperature vacuum annealing and post metal annealing (PMA) treatments. Moreover, the endurance and retention properties of the device were also improved after the PMA treatment. (c) 2015 AIP Publishing LLC.
Random Telegraph Noise in 1X-nm CMOS Silicide Contacts and a Method to Extract Trap Density
(2012-04-01)
Chen, Min-Cheng
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Lin, Chia-Yi
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Chen, Bo-Yuan
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Lin, Chang-Hsien
;
Huang, Guo-Wei
The behavior of random telegraph noise was affected by nickel silicide barrier height engineering in advanced nano-CMOS technologies. Contact resistance fluctuations with magnitude of up to 40% were observed when a Schottky barrier was reduced to 0.2 eV. The large contact resistance instability is attributed to the barrier modification by positive charge trapping and detrapping in a Schottky contact. The prevalence and magnitude of the noise are dependent on the contact area, trap density, trap energy, and the silicide Schottky barrier height. In this letter, we propose a fast method to extract the density of responsible contact traps.