Browsing by Author "Ho, JH"

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A new observation of the germanium outdiffusion effect on the hot carrier and NBTI reliabilities in sub-100nm technology strained-Si/SiGe CMOS devices
(2005)
Chung, SS
;
Liu, YR
;
Yeh, CF
;
Wu, SR
;
Lai, CS
In this paper, the evidence of SiGe layer induced trap generation and its correlation with enhanced degradation in strained-Si/SiGe CMOS devices have been reported for the first time. First, a new two-level charge pumping(CP) curve has been demonstrated to identify the Ge out-diffusion effect. Secondly, enhanced degradation in strained-Si devices has been clarified based on experimental results. Both n- and p-MOSFE's exhibit different extent of HC degradation effect. This is attributed to the difference in their mobility enhancement as well as additional traps coming from the Si/SiGe interface. Finally, temperature dependence of HC and NBTI has been examined for both strained-Si and bulk devices. Sophisticated measurement techniques, charge pumping and gated-diode (GD) measurements, have been employed to understand the generated interface traps. Results show that strained-Si device is less sensitive to the temperature and has a chance for better NBTI reliability if we have a good control of the strained-Si/SiGe interface, such as through low temperature gate oxide process or better S/D junction formation.
Low leakage reliability characterization methodology for advanced CMOS with gate oxide in the 1nm range
(2004)
Chung, SS
;
Feng, HJ
;
Hsieh, YS
;
Liu, A
;
Lin, WM
A low leakage characterization technique for the lateral profiling of interface and oxide traps in a 12Angstrom-16Angstrom range gate oxide CMOS devices has been demonstrated. The approach being taken includes an incremental frequency Charge-Pumping(IFCP) measurement and a neutralization procedure such that interface and oxide traps can be separated. The most critical steps are the elimination of leakage current during measurement and a neutralization procedure, which enables accurate detennination of interface and oxide traps. This method has been demonstrated successfully for an advanced sub-100nm CMOS devices. As an important merit for its application, evaluations of HC reliability and NBTI effect have also been demonstrated. Evaluations of gate oxide qualities with plasma nitridation in both n- and p-MOSFET reliabilities have been properly described based on the current analysis technique.