Browsing by Author "Ho, Y. H."

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Device Instability of ReRAM and a Novel Reference Cell Design for Wide Temperature Range Operation
(2017-09-01)
Lin, Y. H.
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Lin, Y. Y.
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Lee, F. M.
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Ho, Y. H.
;
Hsu, K. C.
This letter addresses two difficult challenges for transition metal oxide resistive random access memories (ReRAMs)-sensitivity to operation temperature and random fluctuation of resistance value. A careful study of a WOx ReRAM array reveals that these devices are unstable and their read currents fluctuate with time due to random telegraph noise and structure relaxation. Consequently, even after careful programming, the current distribution can broaden with time and tail bit population grows. Furthermore, ReRAM state is sensitive to temperature and a reference cell made of the same device material must be used. Thus, although the broadening of read current distribution may be tolerated by creating a larger RESET/SET memory window, the current fluctuation still makes it impossible to predict the output of the reference cell, leading to array malfunction. This letter investigates the current (resistance) instability in detail and proposes a reference array with a novel trimming method that can stabilize the reference current level. The proposed reference array has very good dc stress reliability as well as wide-range temperature tracking performance from -40 degrees C to 85 degrees C.
The investigation of charge loss mechanism in a two-bit wrapped-gate nitride storage nonvolatile memory
(2010-11-01)
Ho, Y. H.
;
Chung, Steve S.
;
Chen, H. H.
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The charge loss mechanism of a two-bit wrapped-gate nitride storage nonvolatile memory is investigated. From retention measurements, it was shown that both vertical and lateral charge loss coexist. As a result of the misalignment of carriers, the lateral charge loss was caused by the hole accumulation near the junction and migrating toward the channel. By using a scaling of the word-gate length or a substrate-transient hot hole erase scheme, the charge loss in the lateral direction can be suppressed. Also, from the retention test, the latter scheme, substrate-transient hot hole (STHH), has a window independent of the word-gate length, which is better for the device scaling. (C) 2010 American Institute of Physics. [doi:10.1063/1.3508956]
The investigation of charge loss mechanism in a two-bit wrapped-gate nitride storage nonvolatile memory
(2010-11-01)
Ho, Y. H.
;
Chung, Steve S.
;
Chen, H. H.
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The charge loss mechanism of a two-bit wrapped-gate nitride storage nonvolatile memory is investigated. From retention measurements, it was shown that both vertical and lateral charge loss coexist. As a result of the misalignment of carriers, the lateral charge loss was caused by the hole accumulation near the junction and migrating toward the channel. By using a scaling of the word-gate length or a substrate-transient hot hole erase scheme, the charge loss in the lateral direction can be suppressed. Also, from the retention test, the latter scheme, substrate-transient hot hole (STHH), has a window independent of the word-gate length, which is better for the device scaling. (C) 2010 American Institute of Physics. [doi:10.1063/1.3508956]