Browsing by Author "Hong, Chi-Hao"

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A 28nm 36kb High Speed 6T SRAM with Source Follower PMOS Read and Bit-Line Under-Drive
(2015)
Hong, Chi-Hao
;
Chiu, Yi-Wei
;
Zhao, Jun-Kai
;
Jou, Shyh-Jye
;
Wang, Wen-Tai
In this paper, we present source follower PMOS Read and bit-line under-drive techniques to improve the operation speed as compared to present commercial SRAM compilers. A source follower PMOS is utilized to connect local bit-lines (LBL) to global bit-lines (GBL) instead of using a NAND gate. To further improve the discharging time from LBL to GBL, we propose a bit-line under-drive circuit to reduce the voltage level of LBL. The simulated access time of the proposed macro is 445 ps at slow N slow P (SS) corner, -40 degrees C, 0.81 V. As compared to the SRAM macro which is generated by commercial SRAM compilers with the fastest combination, the access time of the proposed SRAM macro is 12% faster than that of commercial SRAM compilers. A 36kb high speed 6T SRAM macros with source follower PMOS Read and bit-line under-drive techniques is fabricated in 28nm HKMG CMOS process. The measurement results of the chip in SS corner show the proposed SRAM macro passes all MBIST patterns at 500 MHz at 0.81 V, room temperature.
Robustness Enhancement of a Class-C Quadrature Oscillator Using Capacitive Source Degeneration Coupling
(2015-01-01)
Hong, Chi-Hao
;
Wu, Chuan-Yi
;
Liao, Yu-Te
;
資訊工程學系
;
Department of Computer Science
This brief presents a low-phase-noise Class-C-type quadrature voltage-controlled oscillator (QVCO) with a robust start-up. The chip was implemented using the 0.18-mu m CMOS technology. A source degeneration coupling technique is used to generate quadrature signals and enables the elimination of bimodal oscillation. Capacitive degeneration coupling also provides negative impedance to compensate for losses in the LC tank, resulting in less power consumption in the core circuit to sustain oscillation. The proposed 2.4-GHz QVCO design achieves a 13.46% tuning range and a phase noise of -128.65 dBc/Hz at a 1-MHz offset while only consuming 2.67 mW from a 1.8-V supply. The oscillator demonstrated robust operation from -25 degrees C to 85 degrees C with phase noise lower than -122 dBc/Hz at a 1-MHz offset. The proposed QVCO achieves a remarkable figure of merit of -192 dBc/Hz.