Browsing by Author "Hong, Yu-Ju"

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Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture
(2009-12-01)
Huang, Ya-Shih
;
Hong, Yu-Ju
;
Huang, Juinn-Dar
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In deep-submicron technology, several state-of-the-art architectural synthesis flows have already adopted the distributed register architecture to cope with the increasing wire delay by allowing multicycle Communication. In this article, we regard communication synthesis targeting a refined regular distributed register architecture, named RDR-GRS, as a problem of simultaneous data transfer routing and scheduling for global interconnect resource minimization. We also present an innovative algorithm with regard of both spatial and temporal perspectives. It Features both a concentration-oriented path router gathering wire-sharable data transfers and a channel-based time scheduler resolving contentions for wires in a channel, which are in spatial and temporal domain, respectively. The experimental results show that the proposed algorithm can significantly outperform existing related works.
Simultaneous Data Transfer Routing and Scheduling for Interconnect Minimization in Multicycle Communication Architecture
(2009)
Hong, Yu-Ju
;
Huang, Ya-Shih
;
Huang, Juinn-Dar
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In deep submicron technology, wire delay is no longer negligible and is gradually becoming a dominant factor of system performance. Several state-of-the-art architectural synthesis flows have already adopted the distributed register architecture to cope with the increasing wire delay by allowing multicycle communication. In this paper, we formulate channel and register allocation within a refined regular distributed register architecture, named RDR-GRS, as a problem of simultaneous data transfer routing and scheduling for minimizing global interconnect resources. We also present an innovative algorithm with both spatial and temporal considerations. It features both a concentration-oriented path router gathering wire-sharable data transfers and a channel-based time scheduler resolving contentions for wires in a channel, which are in spatial and temporal domain, respectively. The experimental results show that the proposed algorithm can significantly outperform existing related works.