Browsing by Author "Hong, Zheng-Hao"

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A 3.12 pJ/bit, 19-27 Gbps Receiver with 2 Tap-DFE Embedded Clock and Data Recovery
(2014)
Hong, Zheng-Hao
;
Chen, Wei-Zen
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 19-27-Gb/s receiver comprising of a continuous time linear equalizer (CTLE) followed by a 2 tap decision feedback equalizer embedded clock and data recovery circuit is implemented. The hybrid CDR is operated at half rate, which is incorporated into a broad band PLL to facilitate ISI and jitter suppression over wide band operation. A quadrature relaxation type oscillator is proposed to provide the sampling phases without bulky inductors. Fabricated in a 40 nm CMOS technology, the whole receiver manifests a high energy efficiency of 3.12pJ/bit at 27 Gbps operation to compensate 20 dB channel loss at Nyquist frequency. The core area is 0.09 mm(2) only.
A 3.12 pJ/bit, 19-27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery
(2015-11-01)
Hong, Zheng-Hao
;
Liu, Yao-Chia
;
Chen, Wei-Zen
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 19-27 Gbps receiver comprised of a continuous-time linear equalizer (CTLE) followed by a 2-tap decision feedback equalizer embedded clock and data recovery circuit is implemented. The hybrid CDR is operated at half rate, which is incorporated into a broadband PLL to facilitate ISI and jitter suppression over wide-band operation. To accommodate different channel response, an automatic threshold tracking (ATT) circuit combining with sign-sign least mean square (LMS) adaptive engine is realized. A quadrature relaxation-type oscillator is proposed to provide the sampling phases without bulky inductors. It also provides the advantages of small form factor and wide range operation (19-27 Gbps) to compensate 20 dB channel loss at 12.5 GHz. Fabricated in a 40 nm CMOS technology, the whole receiver manifests an energy efficiency of 3.12 pJ/bit at 27 Gbps operation. The core area is 0.09 mm(2) only.
A 40 Gbps Optical Receiver Analog Front-End in 65 nm CMOS
(2012)
Chou, Shun-Tien
;
Huang, Shih-Hao
;
Hong, Zheng-Hao
;
Chen, Wei-Zen
;
電子工程學系及電子研究所
A 40 Gbps optical receiver analog front end integrating a trans-impedance amplifier (TIA) and a limiting amplifier is presented. To achieve wide band operation, nested feedback TIA and interleaving post amplifier with split series-peaking are proposed in this design. This receiver provides the transimpedance of 92 dBOhm, input-referred noise of 14 pA/root Hz, -3dB bandwidth of 35 GHz, and 800mV(pp) differential output voltage swing. The total power dissipation is 168 mW from 1.2-V supply. Fabricated in a 65 nm CMOS technology, the chip size is 0.825mm(2).