Browsing by Author "Hou, CS"

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A design strategy for short gate length SOI MESFETs
(1996-03-01)
Hou, CS
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A design strategy for short gate length, self-aligned Si-SOI MESFETs is proposed, in which the design considerations for the important device parameters of the SOI MESFET are studied by using a 2D numerical simulator. It is shown that the sub-threshold I-ds-V-gs characteristics can be used to determine the thickness of silicon film for a given channel doping level under a specified threshold voltage. Moreover, the 2D effect can be suppressed by reducing the thickness of buried oxide to improve the bottom-gate controllability over the channel charges. Moreover, it is shown the backgate bias is also an important controllable parameter for modulating the characteristics of the SOI MESFET in both sub-threshold and saturation regions. An example for designing a very short gate length (0.1 mu m) SOI MESFET has been carried out to verify this strategy. It is shown that the proposed strategy does provide an effective procedure for designing an Si-SOI MESFET with high performance.
A novel cross-coupled inter-poly-oxide capacitor for mixed-mode CMOS processes
(1999-07-01)
Chen, MJ
;
Hou, CS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The inter-poly-oxide (IPO) capacitor is one of the main elements in present mixed-mode CMOS process technologies, However, the phenomenon of poly depletion causes a significant change in the measured capacitance with applied voltage, This effect, expressed in terms of the voltage coefficient of capacitance (VCC), can seriously deteriorate analog precision. In this letter, a novel cross-coupled scheme is proposed for the IPO capacitors. The resulting VCC has a very low measured value of 2 ppm/V in a 0.35-mu m standard mixed-mode CMOS process, achieved without any unconventional approaches.
A physical model for the correlation between holding voltage and holding current in epitaxial CMOS latch-up
(1998-08-01)
Chen, MJ
;
Lee, HS
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Chen, JH
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Hou, CS
;
Lin, CS
A new physical model concerning the holding points for latch-up in epitaxial CMOS structures is established by combining the lateral p-i-n high level injection and the vertical BJT base push-out formula. The model matches adequately the correlation between holding voltage and holding current extensively measured from different combinations of temperatures, epitaxial layer thicknesses, and anode-to-cathode spacings, This is also the case for the two-dimensional device simulations. A quantitative analysis based on the model consistently judges the crucial role of the vertical BJT base push-out width in producing the observed correlation. The potential merits of the model in extended applications are outlined.
A trap generation closed-form statistical model for intrinsic oxide breakdown
(2001-06-01)
Huang, HT
;
Chen, MJ
;
Su, CW
;
Chen, JH
;
Hou, CS
A trap generation statistical model with the trap sphere radius r as parameter has been newly formulated in closed-form for intrinsic breakdown of ultrathin oxides and, by incorporating the trap filling fraction p as the secondary parameter, can be practically useful in a manufacturing process. Experimental reproduction for different oxide thicknesses and areas has been achieved through the model. A certain criterion has readily been drawn from the model, with which the ultimate thickness limit for breakdown can be set.
Back-gate bias enhanced band-to-band tunneling leakage in scaled MOSFET's
(1998-04-01)
Chen, MJ
;
Huang, HT
;
Hou, CS
;
Yang, KN
;
電子工程學系及電子研究所
The drain leakage current in MOSFET's in the present standard process is separated into three distinct components: the subthreshold conduction, the surface band-to-band tunneling (BTBT), and the bulk BTBT, Each of the three shows different dependencies on hack-gate bias, As a result, the hulk BTBT, increasing exponentially with increasing the magnitude of back-gate reverse bias, promptly dominates the drain leakage, Additional experiment highlights the effect of the increased hulk dopant concentrations as in next-generation scaled MOSFET's on the bulk BTBT, This sets the hulk BTBT a significant constraint to the low-voltage. low-power, high-density circuits employing the back-gate reverse bias, In the work, the measured drain leakage of interest is successfully reproduced by two-dimensional (2-D) device simulation.
Impact of a large earthquake on a GPS network: The case of the 1999 Chi-Chi, Taiwan earthquake
(2002-04-01)
Kuo, LC
;
Yu, SB
;
Hsu, VJ
;
Hou, CS
;
Lee, YH
On 20 September 1999, Taiwan was hit by the largest inland earthquake (M-w = 7.6) in the last century resulting in an 80-kilometre thrust rupture almost directly along the existing Chelungpu fault. Here, we estimated the coordinates of the GPS stations by using the annual epoch-observed and permanent continuously-recorded GPS data covering the 1992-1999 period Taking into account the effects of secular motion and post-deformation, we calculated the corrected coseismic displacements. Relatively large coseismic displacements of 8-9 in in the horizontal and vertical components were found in the northern part of the fault. Stations on the hanging wall shifted horizonatly 2-9 in in the NW direction and decreased in magnitude from west to east. On the other hand, displacements on the footwall were less than 2 in in the SE direction hid increased from west to east. The size of the zone overlapping the hanging wall and the foowall showed a decrease of 796 ppm in 494 km(2). This is in direct contrast to areas near the fault which increased in size from 13 to 23 7 ppm. Significant postseismic deformations were also observed in data from the existing 44 permanent stations and 7 temporary stations. Additionally, large postseismic deformations of 10-20 cm were found at stations SUAM, 100 7 and YUSN within 10 months.
Monte Carlo sphere model for effective oxide thinning induced extrinsic breakdown
(2000-04-01)
Huang, HT
;
Chen, MJ
;
Chen, JH
;
Su, CW
;
Hou, CS
The Monte Carlo sphere model is extended to deal with the extrinsic time-dependent-dielectric-breakdown (TCDB) by incorporating the well-known "effective oxide thinning" concept. Percolation simulation, based on this model for the first time, evidences that the process defects induced extrinsic TDDB is also statistical in nature as is the intrinsic one, and is characterized by a probability function defining local oxide thinning. The experimental bimodal or even multimodal characteristics can be reproduced accordingly. Furthermore, the simulation results in the extrinsic regime are found to be sample-size (i.e., the total number of samples that span the breakdown statistics) dependent, suggesting that care should be taken when evaluating the extrinsic TDDB data in a real manufacturing process.