Browsing by Author "Hou, TH"

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Effects of base oxide in HfSiO/SiO2 high-k gate stacks
(2004)
Wu, WH
;
Chen, MC
;
Wang, MF
;
Hou, TH
;
Yao, LG
Electrical characteristics of HfSiO/SiO2 high-k gate stacks have been extensively explored with regard to the effects of base oxide. The flatband voltage shift in N/PMOS capacitors is independent of base oxide thickness, and the dielectric breakdown of the gate stacks is determined by base oxide. In addition, base oxide thickness has a great impact on device performance and charge trapping, presumably due to remote Coulomb scattering (RCS) in the HfSiO bulk layer and direct tunneling through the base oxide. Threshold voltage instability induced by charge trapping will be a major reliability concern for Hf-based high-k gate dielectrics in the future.
Improvement of junction leakage of nickel silicided junction by a Ti-capping layer
(1999-11-01)
Hou, TH
;
Lei, TF
;
Chao, TS
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel NiSi process with a thin Ti-cap layer is proposed, for the first time, to improve the leakage problem of Ni-silicided junction, The Ti-cap samples exhibit a very low leakage current density about 1 x 10 A/cm(2) after 600 degrees C annealing, which is one order of magnitude reduction comparing with uncapped samples. From Anger analyzes, it is found that this significant improvement results from suppression of the oxidation of the Ni-silicide during the thermal annealing process.