Browsing by Author "Hou, Tuo-Hung"

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1-V Full-Swing Depletion-Load a-In-Ga-Zn-O Inverters for Back-End-of-Line Compatible 3D Integration
(2016-04)
Chi, Li-Jen
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Yu, Ming-Jiue
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Chang, Yu-Hong
;
Hou, Tuo-Hung
;
電子工程學系及電子研究所
To enable monolithic three-dimensional integration of the amorphous In-Ga-Zn-O (a-IGZO) and CMOS technologies, the a-IGZO inverters compatible with the low operating voltage (<= 1 V) and process temperature of back-end-of-line CMOS have been investigated. We demonstrated a full-swing depletion-load inverter with a voltage gain up to 24 using a CMOS-compatible operating voltage of 1 V. The drive transistor was realized using a low-voltage enhancement-mode a-IGZO thin-film transistor (TFT) with a steep subthreshold swing of 70 mV/decade and a low threshold voltage of 0.5 V. The load transistor was implemented using a bi-layer a-IGZO channel, where the a-IGZO composition was modulated simply by the oxygen flow rate in a depletion-mode TFT.
32-nm Multigate Si-nTFET With Microwave-Annealed Abrupt Junction
(2016-05)
Hou, Fu-Ju
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Sung, Po-Jung
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Hsueh, Fu-Kuo
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Wu, Chien-Ting
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Lee, Yao-Jen
Microwave annealing (MWA) activates dopants through solid-phase epitaxial regrowth with low thermal budget. Optimizing the microwave power during MWA is capable of realizing low defect density at the junction, suppressing the dopant diffusion, and mitigating the straggle effect of ion implantation. These favorable features of MWA facilitate the formation of extremely abrupt junction profiles in tunnel FETs (TFETs). In conjunction with the improved gate-to-channel controllability of the multiple-gate (MG) structure, we demonstrate high-performance lateral n-type Si-TFETs using a CMOS-compatible process flow with excellent band-to-band tunneling efficiency and device scalability. The 32-nm MG Si-TFET shows promising characteristics, including a high ON-state current of 41.3 mu A/mu m, a large current ON/OFF ratio of > 5 x 10(7), and minimal short-channel effect using V-G = 2 V and V-D = 1 V.
3D resistive RAM cell design for high-density storage class memory-a review
(2016-06)
Hudec, Boris
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Hsu, Chung-Wei
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Wang, I-Ting
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Lai, Wei-Li
;
Chang, Che-Chia
In this article, we comprehensively review recent progress in the ReRAM cell technology for 3D integration focusing on a material/device level. First we briefly mention pioneering work on high-density crossbar ReRAM arrays which paved the way to 3D integration. We discuss the two main proposed 3D integration schemes-3D horizontally stacked ReRAM vs 3D Vertical ReRAM and their respective advantages and disadvantages. We follow with the detailed memory cell design on important work in both areas, utilizing either filamentary or interface-limited switching mechanisms. We also discuss our own contributions on HfO2-based filamentary 3D Vertical ReRAM as well as TaOx/TiO2 bilayer-based self-rectifying 3D Vertical ReRAM. Finally, we summarize the present status and provide an outlook for the nearterm future.
3D Synaptic Architecture with Ultralow sub-10 fJ Energy per Spike for Neuromorphic Computation
(2014)
Wang, I-Ting
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Lin, Yen-Chuan
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Wang, Yu -Fen
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Hsu, Chung-Wei
;
Hou, Tuo-Hung
A high-density 3D synaptic architecture based on self-rectifying Ta/TaOx/TiO2/Ti RRAM is proposed as an energy- and cost-efficient neuromorphic computation hardware. The device shows excellent analog synaptic features that can be accurately described by the physical and compact models. Ultra-low energy consumption comparable to that of a biological synapse (<10 fJ/spike) has been demonstrated for the first time.
3D Ta/TaOx/TiO2/Ti synaptic array and linearity tuning of weight update for hardware neural network applications
(2016-09-09)
Wang, I-Ting
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Chang, Chih-Cheng
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Chiu, Li-Wen
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Chou, Teyuh
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Hou, Tuo-Hung
The implementation of highly anticipated hardware neural networks (HNNs) hinges largely on the successful development of a low-power, high-density, and reliable analog electronic synaptic array. In this study, we demonstrate a two-layer Ta/TaOx/TiO2/Ti cross-point synaptic array that emulates the high-density three-dimensional network architecture of human brains. Excellent uniformity and reproducibility among intralayer and interlayer cells were realized. Moreover, at least 50 analog synaptic weight states could be precisely controlled with minimal drifting during a cycling endurance test of 5000 training pulses at an operating voltage of 3 V. We also propose a new state-independent bipolar-pulse-training scheme to improve the linearity of weight updates. The improved linearity considerably enhances the fault tolerance of HNNs, thus improving the training accuracy.
3D Vertical TaOx/TiO2 RRAM with over 10(3) Self-Rectifying Ratio and Sub-mu A Operating Current
(2013-01-01)
Hsu, Chung-Wei
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Wan, Chia-Chen
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Wang, I-Ting
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Chen, Mei-Chin
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Lo, Chun-Li
The 3D double-layer vertical RRAM with ultralow sub-mu A operating current and high self-rectifying ratio over 10(3) has been demonstrated for the first time. This Ta/TaOx/TiO2/Ti interfacial switching device overcomes the intrinsic trade-off between operating current and variability in filamentary RRAMs and shows promising potential for high-density data storage.
A Comprehensive Modeling Framework for Ferroelectric Tunnel Junctions
(2019-01-01)
Huang, Hsin-Hui
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Wu, Tzu-Yun
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Chu, Yueh-Hua
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Wu, Ming-Hung
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Hsu, Chien-Hua
A modeling framework for ferroelectric tunnel junctions (FTJs) that considers nonpolar interfacial layers (ILs), multi-domain polarization, and complete ferroelectric/capacitive/tunneling currents simultaneously is proposed. This model explains both read and write operations including the controversial switching polarities of FTJ. We also provide useful guidelines for optimizing FTJ performance where the location of IL and the effective thickness ratio between ferroelectric and interfacial layers are found to be most critical.
A Fluorographene-Based Synaptic Transistor
(2019-08-13)
Liu, Bo
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Hong, Ming-Chun
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Sahoo, Mamina
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Ong, Bin Leong
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Tok, Eng Soon
Exploring brain-inspired synaptic devices has recently become a new focus of research in nanoelectronic communities. In this emerging field, incorporating 2D materials into three-terminal synaptic transistors has brought various advantages. However, achieving a stable and long-term weight-modulation in these synaptic transistors, which are typically based on interface charge storage, is still a challenge due to the nature of their spontaneous relaxation. The application of an atomically thin fluorographene layer into the synaptic junction region suppresses this issue and improves the efficiency, tunability, and symmetry of the synaptic plasticity as well as establishing a stable weight-regulation paradigm. These unique properties can be attributed to the dipolar rotation of C-F in fluorographene. To obtain a better physical understanding, a vacancy-dependent C-F dipolar rotation model is proposed and supported by hysteresis analysis and density functional theory calculations. As proposed and demonstrated, the unique fluorographene-based synaptic transistor may be a promising building block for constructing efficient neuromorphic computing hardware.
A Study of Blocking and Tunnel Oxide Engineering on Double-Trapping (DT) BE-SONOS Performance
(2015)
Lo, Roger
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Du, Pei-Ying
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Hsu, Tzu-Hsuan
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Wu, Chen-Jun
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Guo, Jung-Yi
Double-trapping bandgap engineered SONOS (DT BE-SONOS) [1] was proposed to provide both fast erase speed and deep erase by means of a second nitride trapping layer and an additional blocking oxide on top of BE-SONOS. Although this provides excellent erase performance but the additional layers increase the EOT and subsequently the erase voltage, thus it is desirable to minimize their impact. This work investigates exhaustively the effect of thinning down the blocking layers. Since the ISPP and high temperature retention charge loss are mainly dominated by the ONO thickness of BE-SONOS below the blocking layers, reducing the blocking layer thickness has only minor impact on ISPP and retention. Moreover, erase saturation is determined by the dynamic balance of channel hole injection and gate electron injection. Experimental data show that reducing the thickness of the oxide between two trapping layers has little impact on erase saturation once the gate injected electrons are efficiently suppressed by the top most oxide. We have also investigated retention improvement by various oxides. By using HQ-SiO2 to replace the top tunnel ONO the trapped electron out-tunneling is reduced. Thus retention may be improved without increasing the effective oxide thickness.
Abnormal positive bias stress instability of In-Ga-Zn-O thin-film transistors with low-temperature Al2O3 gate dielectric
(2016-01-18)
Chang, Yu-Hong
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Yu, Ming-Jiue
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Lin, Ruei-Ping
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Hsu, Chih-Pin
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Hou, Tuo-Hung
Low-temperature atomic layer deposition (ALD) was employed to deposit Al2O3 as a gate dielectric in amorphous In-Ga-Zn-O thin-film transistors fabricated at temperatures below 120 degrees C. The devices exhibited a negligible threshold voltage shift (Delta V-T) during negative bias stress, but a more pronounced Delta V-T under positive bias stress with a characteristic turnaround behavior from a positive Delta V-T to a negative Delta V-T. This abnormal positive bias instability is explained using a two-process model, including both electron trapping and hydrogen release and migration. Electron trapping induces the initial positive Delta V-T, which can be fitted using the stretched exponential function. The breakage of residual AlO-H bonds in low-temperature ALD Al2O3 is triggered by the energetic channel electrons. The hydrogen atoms then diffuse toward the In-Ga-Zn-O channel and induce the negative Delta V-T through electron doping with power-law time dependence. A rapid partial recovery of the negative Delta V-T after stress is also observed during relaxation. (C) 2016 AIP Publishing LLC.
AC stress and electronic effects on SET switching of HfO2 RRAM
(2017-08-28)
Liu, Jen-Chieh
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Magyari-Kope, Blanka
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Qin, Shengjun
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Zheng, Xin
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Wong, H. -S. Philip
An AC stress test was performed to investigate the accompanying electronic effects in a HfO2 resistive random access memory during the SET transition, which featured a sudden decrease in resistance. Comparing the DC and AC measurement results indicated the pronounced influence of interrupted stress on both the mean values and variations of time to SET. First-principles calculations suggested that the charge states (+2, +1, or neutral) of oxygen vacancies affect the migration barrier for forming oxygen vacancy clusters. Therefore, a charge-state-dependent SET model is proposed to include the additional electronic effects induced by the dynamics of electron trapping and detrapping in oxygen vacancies during AC stress. A trimodal Weibull fitting based on the proposed model reproduced the experimental time to SET distributions obtained in a wide range of AC stress conditions. Published by AIP Publishing.
Amorphous InGaZnO Thin-Film Transistors Compatible With Roll-to-Roll Fabrication at Room Temperature
(2012-01-01)
Yu, Ming-Jiue
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Yeh, Yung-Hui
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Cheng, Chun-Cheng
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Lin, Chang-Yu
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Ho, Geng-Tai
High-performance amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) are successfully fabricated on a colorless polyimide substrate using a top-gate self-aligned structure. All thin films are deposited by roll-to-roll-compatible sputtering processes at room temperature. The maximum field-effect mobility is 18 cm(2)/V . s, the threshold voltage is - 1.35 V, the subthreshold slope is 0.1 V/decade, and the on/off current ratio is about 10(5). The results highlight that excellent device performance can be realized in a-IGZO TFTs without compromising manufacturability.
Bipolar Ni/TiO2/HfO2/Ni RRAM With Multilevel States and Self-Rectifying Characteristics
(2013-07-01)
Hsu, Chung-Wei
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Hou, Tuo-Hung
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Chen, Mei-Chin
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Wang, I-Ting
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Lo, Chun-Li
To be compatible with 3-D vertical crossbar arrays, a TiO2/HfO2 bilayer resistive-switching memory (RRAM) cell sandwiched between Ni electrodes is developed. The proposed device has numerous highly desired features for the implementation of 3-D vertical RRAM, including: 1) stable bipolar resistive switching; 2) forming free; 3) self-compliance; 4) self-rectification; 5) multiple resistance states; and 6) room-temperature process. The resistive switching and current rectification are attributed to oxygen vacancy migration in HfO2 and potential barrier modulation of the asymmetric TiO2/HfO2 tunnel barrier. The rectification ratio up to 10(3) is capable of realizing a single-crossbar array up to 16 Mb for future high-density storage class memory applications.
Bipolar Nonlinear Ni/TiO(2)/Ni Selector for 1S1R Crossbar Array Applications
(2011-10-01)
Huang, Jiun-Jia
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Tseng, Yi-Ming
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Hsu, Chung-Wei
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Hou, Tuo-Hung
;
電子工程學系及電子研究所
A bipolar nonlinear selector to suppress the sneak current in the crossbar array has been fabricated using a simple Ni/TiO(2)/Ni metal-insulator-metal structure. The highly nonlinear current-voltage characteristics are realized by the Schottky emission over the Ni/TiO(2) barriers. The series connection with an HfO(2)-resistive memory device shows reproducible bipolar resistive switching. The maximum array size with at least 10% read margin is projected to exceed megabits. This letter demonstrates the promise of the compact one selector-one resistor (1S1R) cell structure for high-density crossbar array applications.
Bipolar Nonlinear Ni/TiO2/Ni Selector for 1S1R Crossbar Array Applications
(2011-10-01)
Huang, Jiun-Jia
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Tseng, Yi-Ming
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Hsu, Chung-Wei
;
Hou, Tuo-Hung
;
電子工程學系及電子研究所
A bipolar nonlinear selector to suppress the sneak current in the crossbar array has been fabricated using a simple Ni/TiO2/Ni metal-insulator-metal structure. The highly nonlinear current-voltage characteristics are realized by the Schottky emission over the Ni/TiO2 barriers. The series connection with an HfO2-resistive memory device shows reproducible bipolar resistive switching. The maximum array size with at least 10% read margin is projected to exceed megabits. This letter demonstrates the promise of the compact one selector-one resistor (1S1R) cell structure for high-density crossbar array applications.
Categorization of Multilevel-Cell Storage-Class Memory: An RRAM Example
(2015-08-01)
Liu, Jen-Chieh
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Hsu, Chung-Wei
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Wang, I-Ting
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Hou, Tuo-Hung
;
電子工程學系及電子研究所
This paper provides new insights into the effect of device characteristics on multilevel-cell (MLC) operation, aiming at potential benefits, such as the reduction of write latency and peripheral circuit design overhead. A general categorization of the MLC-operating schemes in storage-class memory (SCM) is proposed to connect the total number of write inputs with fundamental device properties. The categorization method is validated using two resistive random access memory devices based on different switching mechanisms. Favorable device characteristics and the corresponding simplified MLC operating schemes are addressed to facilitate future development of MLC SCM.
Challenges and Opportunities toward Online Training Acceleration using RRAM-based Hardware Neural Network
(2017-01-01)
Chang, Chih-Cheng
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Liu, Jen-Chieh
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Shen, Yu-Lin
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Chou, Teyuh
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Chen, Pin-Chun
This paper highlights the feasible routes of using resistive memory (RRAM) for accelerating online training of deep neural networks (DNNs). A high degree of asymmetric nonlinearity in analog RRAMs could be tolerated when weight update algorithms are optimized with reduced training noise. Hybrid-weight Net (HW-Net), a modified multilayer perceptron (MLP) algorithm that utilizes hybrid internal analog and external binary weights is also proposed. Highly accurate online training could be realized using simple binary RRAMs that have already been widely developed as digital memory.
Characterization and Modeling of Nonfilamentary Ta/TaOx/TiO2/Ti Analog Synaptic Device
(2015-05-08)
Wang, Yu-Fen
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Lin, Yen-Chuan
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Wang, I-Ting
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Lin, Tzu-Ping
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Hou, Tuo-Hung
A two-terminal analog synaptic device that precisely emulates biological synaptic features is expected to be a critical component for future hardware-based neuromorphic computing. Typical synaptic devices based on filamentary resistive switching face severe limitations on the implementation of concurrent inhibitory and excitatory synapses with low conductance and state fluctuation. For overcoming these limitations, we propose a Ta/TaOx/TiO2/Ti device with superior analog synaptic features. A physical simulation based on the homogeneous (nonfilamentary) barrier modulation induced by oxygen ion migration accurately reproduces various DC and AC evolutions of synaptic states, including the spike-timing-dependent plasticity and paired-pulse facilitation. Furthermore, a physics-based compact model for facilitating circuit-level design is proposed on the basis of the general definition of memristor devices. This comprehensive experimental and theoretical study of the promising electronic synapse can facilitate realizing large-scale neuromorphic systems.
Characterization of Highly Strained nFET Device Performance and Channel Mobility with SMT
(2010)
Lu, Chih-Cheng
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Huang, Jiun-Jia
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Luo, Wun-Cheng
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Hou, Tuo-Hung
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Lei, Tan-Fu
This paper compares and analyzes the strained negative channel field effect transistor (nFET) device performance and the channel mobility behavior obtained by the stress memorization technique (SMT) using two different types of nitride films. These nitride film properties and wafer bowing during SMT fabrication are investigated. The electrical properties of SMT strained nFET devices including current-voltage characteristics, transconductance, carrier mobility, and interface state (D(it)) are also analyzed. Although SMT nitride strain can enhance electron mobility, it is critical to control the nitride properties and its hydrogen content to minimize electron mobility degradation due to interface-state generation. Thus, a simple view of the essential physics of mobility enhancement in SMT strained nFETs has been provided. Results in this work also provide guidance to further nFET performance enhancement in the ever-more challenging device targets of future technology generations. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3416923] All rights reserved.
Crossbar array of selector-less TaOx/TiO2 bilayer RRAM
(2015-11-01)
Chou, Chun-Tse
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Hudec, Boris
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Hsu, Chung-Wei
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Lai, Wei-Li
;
Chang, Chih-Cheng
In this work, we have implemented self-rectifying TaOx/TiO2 REAM in a selector-less 6 x 6 crossbar array with various desiring features, including: (1) simple fabrication using only three masks, (2) high self-rectifying ratio up to 10(3) for sneak current suppression, (3) stable bipolar resistive-switching characteristics without the need for electro-forming and current compliance, (4) data retention time over 10(4) s, and (5) robust READ and WRITE disturb immunity. Finally, an achievable array size of 1 Mb was simulated using an All-LPU read scheme and a V/3 write scheme. (C) 2015 Elsevier Ltd. All rights reserved.