Browsing by Author "Hou, Tzu-Ching"

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Demonstrating 1 nm-oxide-equivalent-thickness La2O3 and HfO2 multi-layer composite oxides on In0.53Ga0.47As MOS capacitor
(2016-01-08)
Wu, Wen-Hao
;
Lin, Yueh-Chin
;
Hou, Tzu-Ching
;
Lin, Tai-Wei
;
Hsu, Hisang-Hua
The use of a high k composite dielectric composed of La2O3 and HfO2 layers as the gate dielectric for In0.53Ga0.47As MOS application is proposed. Two multi-layer structures of La2O3 (1 nm)/HfO2 (1 nm) and La2O3 (0.5 nm)/HfO2 (0.5 nm) were deposited and annealed at 450 and 500 degrees C for device performance comparison. X-ray photoelectron spectroscopy, TEM and C-V measurements were used for the interface analysis between the oxide and the semiconductor. Finally, a 1 nm equivalent-oxide-thickness dielectric with small hysteresis of 88 mV and D-it of 1.9 x 10(12) cm(-2) eV(-1) was achieved for six layers of an La2O3 (0.5 nm)/HfO2 (0.5 nm) composite oxide structure on an In0.53Ga0.47As MOS capacitor with a post-deposition annealing temperature of 450 degrees C.
Effects of layer sequence and postdeposition annealing temperature on performance of La2O3 and HfO2 multilayer composite oxides on In0.53Ga0.47As for MOS capacitor application
(2014-03-01)
Wu, Wen-Hao
;
Lin, Yueh-Chin
;
Chuang, Ting-Wei
;
Chen, Yu-Chen
;
Hou, Tzu-Ching
In this paper, we report on high-k composite oxides that are formed by depositing multiple layers of HfO2 and La2O3 on In0.53Ga0.47As for MOS device application. Both multilayer HfO2 (0.8 nm)/La2O3 (0.8 nm)/In0.53Ga0.47As and La2O3 (0.8 nm)/HfO2 (0.8 nm)/In0.53Ga0.47As MOS structures were investigated. The effects of oxide thickness and postdeposition annealing (PDA) temperature on the interface properties of the composite oxide MOS capacitors were studied. It was found that a low CET of 1.41 nm at 1 kHz was achieved using three-layer composite oxides. On the other hand, a small frequency dispersion of 2.8% and an excellent D-It of 7.0 Chi 10(11)cm(-2).eV(-1) can be achieved using multiple layers of La2O3 (0.8 nm) and HfO2 (0.8 nm) on the In0.53Ga0.47As MOS capacitor with optimum thermal treatment and layer thickness. (C) 2014 The Japan Society of Applied Physics