Browsing by Author "Hsia, CC"

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Anti-reflection strategies for sub-0.18-mu m dual damascene structure patterning in KrF 248nm lithography
(1999)
Chou, SY
;
Wang, CM
;
Hsia, CC
;
Chen, LJ
;
Hwang, GW
Finding high performance and low cost anti-reflection strategies is a common goal for all photolithographers. This task is getting tough for dual damascene process than the metal-etch process because the oxide thickness variation enhances the thin film interference effect. In this paper, different ARC strategies using organic and inorganic material were examined to compare their CD control performance in sub-0.18 mu m dual damascene structure for KrF 248nm lithography. The organic bottom ARC (BARC) achieves reflectivity control through modulating its thickness. The first and second minimal points in BARC swing curve were chosen as the film thickness to be evaluated. The inorganic ARC, which referred to dielectric ARC (DARC) using PECVD silicon oxynitride (SiOxNy) in this article, was investigated with single layer and double layer structures. The double-layer DARC structure consists of two layers with different extinction coefficient K values. The optimal refractive index (N, K) and thickness of each ARC structure were calculated from some available photolithography simulators. A PECVD process for DARC growth chat provides easily tunable range of refractive index and thickness was established to meet the DW process requirement fr om simulation. The performances of each ARC structure were evaluated on patterning 0.18 mu m trench and 0.20 mu m via in back-end-of-line (BEOL) dual damascene process. It showed that the double-layer DARC provided the most effective CD control ability among these ARC structures. The double-layer DARC should be one of the most potential candidates for sub-0.18 mu m dual damascene process.
Plasma charging damage during contact hole etch in high-density plasma etcher
(2000-12-01)
Tsui, BY
;
Lin, SS
;
Tsai, CS
;
Hsia, CC
;
電子工程學系及電子研究所
Plasma process induced damage from high-density plasma dielectric etcher was studied comprehensively. It was observed that PMOS devices were damaged more readily than NMOS devices. Low field gate current is the most sensitive parameter to reflect the permanent damages. Some permanent damages become hidden defects after backend of line processes. These latent damages in the form of gate oxide traps result in poor oxide integrity during Fowler-Nordheim stress or hot carrier stress. The damage shows good correlation with the total exposed contact area. The safe antenna ratio is much lower than that at the conductor etch, although no electron shading effect was observed. Thus, plasma damage during contact or via hole etch in high-density plasma system must be considered carefully. (C) 2000 Elsevier Science Ltd. All rights reserved.