Browsing by Author "Hsiao, PC"

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Hierarchical instruction encoding for VLIW digital signal processors
(2005)
Liu, CH
;
Lin, TJ
;
Chao, CM
;
Hsiao, PC
;
Lin, LC
VLIW-based architectures are very popular in high-performance DSP processors, for their relatively simpler implementations and more predictable execution times. But they need more program memory because of (1) the fixed-length instruction encoding, (2) NOP insertion due to limited parallelism, and (3) repetitive codes for loop unrolling. This paper describes a novel hierarchical instruction encoding that address these three problems to improve the VLIW code density. In our simulations, the proposed encoding scheme saves 61.4%-66.9% code sizes in highly parallel DSP kernels, and more savings can be expected for general programs. Besides, a simple decoding architecture is proposed and has been integrated into a 4-way VLIW DSP processor. The prototype is implemented in the 0.18um CMOS technology with its operating frequency at 208MHz.
Novel programmable digital signal processor for multimedia applications
(2004)
Lin, LC
;
Lin, TJ
;
Lee, CC
;
Chao, CM
;
Chen, SK
This paper presents a novel DSP architecture for multimedia applications. The DSP core is a simple RISC processor from the programmer's view, which has a high-performance DSP unit and the applications can be easily targeted on the RISC shell to reduce the development time. Moreover, the DSP unit is itself a fully-programmable 4-way VLIW datapath, which has a novel ping-pong register file. To smooth the instruction execution of the two-level programmable DSP processor and improve the code density, we propose a hierarchical encoding scheme for variable-length instructions. The simulations show that our DSP has comparable performance with state-of-the-art DSP architectures, and the hierarchical instruction encoding saves 31%-64% code sizes compared to the fixed-length instruction encoding.