Browsing by Author "Hsiao, SY"

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A 1.2 V CMOS four-quadrant analog multiplier
(1997)
Hsiao, SY
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Wu, CY
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交大名義發表
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電子工程學系及電子研究所
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National Chiao Tung University
A new CMOS four-quadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed new combiner circuit, a low-voltage high-performance CMOS four-quadrant analog multiplier is designed and fabricated by 0.8 mu m N-well double-poly-double-metal CMOS technology. Experimental results have shown that, under single 1.2 V supply voltage, the circuit has 0.89% linearity error and 1.1% total harmonic distortion under the maximum-scale input 500 mV(P-P) at both inputs. The measured -3 dB bandwidth is 2.2 MHz and the power dissipation is 2.8 mW. The input bandwidth of the multiplier can be designed to reach the GHz range. Simple structure, low-voltage low-power capability, and high performance make the proposed multiplier quite feasible in many applications.
A parallel structure for CMOS four-quadrant analog multipliers and its application to a 2-GHz RF downconversion mixer
(1998-06-01)
Hsiao, SY
;
Wu, CY
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A parallel structure for a CMOS four-quadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a low-voltage high-performance CMOS four-quadrant analog multiplier is designed and fabricated by 0.8-mu m N-well double-poly-double-metal CMOS technology, Experimental results have shown that, under a single 1.2-V supply voltage, the circuit has 0.89% linearity error and 1.1% total harmonic distortion under the maximum-scale input 500-mV(P-P) at both multiplier inputs. The -3-dB bandwidth is 2.2 MHz and the dc current is 2.3 mA, By using the proposed multiplier as a mixer-core and connecting a newly designed output buffer, a CMOS RF downconversion mixer is designed and implemented by 0.5-mu m single-poly-double-metal N-well CMOS technology. The experimental results have shown that, under 3-V supply voltage and 2-dBm LO power, the mixer has -1-dB conversion gain, 2.2-GHz input bandwidth, 180- MHz output bandwidth, and 22-dB noise figure. Under the LO frequency 1.9 GHz and the total de current 21 mA, the third order input intercept point is +7.5 dBm and the input 1-dB compression point is -9 dBm.
The design of a 3-V 900-MHz CMOS bandpass amplifier
(1997-02-01)
Wu, CY
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Hsiao, SY
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A new bandpass amplifier which performs both functions of low-noise amplifier (LNA) and bandpass filter (BPF) is proposed for the application of 900-MHz RF front-end in wireless receivers, In the proposed amplifier, the positive-feedback Q-enhancement technique is used to overcome the low-gain low-Q characteristics of the CMOS tuned amplifier, The Miller capacitance tuning scheme is used to compensate for the process variations of center frequency, Using the high-Q bandpass amplifier in the receivers, the conventional bulky off-chip filter is not required, An experimental chip fabricated by 0.8-mu m N-well double-poly-double-metal CMOS technology occupies 2.6 x 2.0 mm(2) chip area, Under a 3 V supply voltage, the measured quality factor is tunable between 2.2 and 44. When the quality factor is tuned at Q = 30, the measured center frequency of the amplifier is tunable between 869-893 MHz with power gain 17 dB, noise figure 6.0 dB, output 1 dB compression point at -30 dBm, third-order input intercept point at -14 dBm, and power dissipation 78 mW.