Browsing by Author "Hsiao, Yu-Chih"

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15 GHz Wideband CMOS Gilbert Up-Converter With Stacked Spiral-CPS Phase-Inverter Rat-Race Coupler at RF Port
(2013)
Hsiao, Yu-Chih
;
Meng, Chinchun
;
Wu, Po-Yi
;
Huang, Guo-wei
;
電機資訊學士班
A miniaturized phase-inverter rat-race and its wideband Gilbert up-converter is demonstrated in 0.13-mu m CMOS technology. The common-mode LO leakage can be absorbed by the isolated port of the rat-race coupler while the rate-race employed at RF port to combine the mixer differential output. A phase-inverter rat-race coupler with a stacked spiral-shape coplanar stripline (CPS) by multi-layer metals can highly reduce the chip size. Finally, the experimental results of up-converter shows the 1-dB conversion gain and 15 GHz RF bandwidth. The IF-to-RF isolation is about 50 dB and LO-to-RF isolation is about 23 dB, respectively.
16-GHz mHEMT Double-Quadrature Gilbert Down-Conversion Mixer With Polyphase Filters
(2013)
Hsiao, Yu-Chih
;
Meng, Chinchun
;
Su, Jen-Yi
;
Yu, Sheng-Wen
;
Huang, Guo-Wei
A 16-GHz double-quadrature very low IF down conversion mixer with polyphase filters is demonstrated using 0.15-nm metamorphic high electron mobility transistor (mHEMT) technology. Due to the hgih cut-off frequency of mHEMT device, the image rejection Gilbert mixer works at 16 GHz. The polyphase filters are employed to generate differential quadrature signals and eliminate the image signal at RF/LO stages and IF stage, respectively, in the double quarture configuration. When RF and LO frequencies are designed around 16 GHz and an IF frequency is 32 MHz, The double-quadrature Gilbert down-converter has 32-dB image rejection ratio, 1.7-dB conversion gain, -5-dBm IP1dB, and 5-dBm IIP3. The die size is 3.0 mm x 3.2 mm.
2.4-GHz Q-Enhanced Lumped Ring Filter With Two Transmission Zeros Using 0.18-mu m SiGe BiCMOS Process
(2017-03-01)
Hsiao, Yu-Chih
;
Meng, Chinchun
;
Yang, Shih-Te
;
電機工程學系
;
Department of Electrical and Computer Engineering
A 2.4-GHz Q-enhanced lumped ring filter with a narrow bandpass response and two stopband-rejection transmission zeros using 0.18-mu m SiGe BiCMOS technology is demonstrated in this letter. A transformer-based Q-enhanced technique is employed to boost the Q-factor of on-chip inductors for low passband insertion loss. The measured results show zero dB insertion loss, 120-MHz 3-dB bandwidth for the passband centered at 2.45 GHz and with two transmission zeros at 2.35 and 2.65 GHz, respectively. The noise figure is about 14.5 dB, IP1dB is about -15.2 dBm and IIP3 is about -4.5 dBm, respectively. The total current consumption is 9.9 mA at 1.8 V supply voltage.
2.4-GHz Tunable Miniature CMOS Active Bandpass Filter With Two Transmission Zeros Using Lumped Stepped-Impedance Ring Resonator
(2018-01-01)
Hsiao, Yu-Chih
;
Meng, Chinchun
;
Chien, Hsieh-Hsiu Chang
;
Huang, Guo-Wei
;
電機工程學系
This paper demonstrates a small-size 2.4-GHz CMOS active bandpass filter with two transmission zeros using a lumped stepped-impedance ring resonator. To obtain low insertion loss and small size, four high-Q active inductors using 0.18 gm CMOS transistors only are employed in the design. The measured insertion loss is 2.9-dB at 2.4 GHz center frequency with two transmission zeros located at 2.1 GHz and 3.1 GHz, respectively. By tuning the bias currents of active inductors, the center frequency has 1.4 GHz tuning range and the 1-dB bandwidth can be adjusted in the range of 190 MHz to 260 MHz. The demonstrated active filter occupies a small chip area of 0.47 mm x 0.33 mm excluding I/O pads and has 24 dB noise figure. Thus, an active filter with a preceding two-stage common-source LNA for suppression of noise of the active filter is also demonstrated and the resulting LNA + active filter has 6 dB noise figure. The power consumption of the active filter core and the LNA core is 9 mW and 7.2 mW, respectively.
5-6 GHz 9.4 mW CMOS Direct-Conversion Passive-Mixer Receiver With Low-Flicker-Noise Corner
(2012-01-01)
Hsiao, Yu-Chih
;
Meng, Chinchun
;
Syu, Jin-Siang
;
Lin, Chung-Yo
;
Wong, Shyh-Chyi
This paper demonstrates a low-power and low-flicker-noise direct-conversion receiver using double-balanced passive mixer. The deep-n-well vertical-NPN bipolar junction transistor is placed as at the input stage of the IF amplifier to reduce the flicker noise in the 0.18 um standard CMOS process. As a result, conversion gain achieves 50-dB gain when the LO power is 10 dBm and the noise figure is 7-dB at 100 kHz. The totally power consumption is 9.4 mW at 1.8 V voltage supply.
5/60 GHz 0.18 mu m CMOS Dual-Mode Dual-Conversion Receiver Using a Tunable Active Filter for 5-GHz Channel Selection
(2016-11)
Hsiao, Yu-Chih
;
Meng, ChinChun
;
Yang, Shih-Te
;
電機工程學系
;
Department of Electrical and Computer Engineering
A dual-mode dual-conversion receiver with two farapart carrier frequencies, 5 and 60 GHz, and two very different channel bandwidths, tens-MHz and GHz, is demonstrated in a standard 0.18 mu m CMOS technology. The dual conversion architecture receives 60-GHz mode using Schottky diodes at the first conversion stage and merges 5-GHz mode at the second conversion stage. The 5-GHz RF channel selection is achieved by inserting a 20-MHz bandwidth tunable active filter after a 5-GHz low-noise amplifier for the noise concern and before the second down-conversion mixer to relax the linearity requirement of subsequent stages. A tunable active filter with improved linearity using a transformer-coupled scheme is employed. As a result, the narrow 20 MHz channel bandwidth selection at 5-GHz mode shows a 500 MHz tuning range with noise figure of 9 dB and conversion gain of 28 dB. For 60-GHz operation, the 3-dB IF bandwidth is 1 GHz with noise figure of about 20 dB and conversion gain of -3 dB.
60-GHz 0.18-mu m CMOS Schottky-Diode Ring-Mixer Down-Converter
(2014)
Hsiao, Yu-Chih
;
Meng, Chinchun
;
Wang, Ta-Wei
;
Huang, Guo-Wei
;
電機學院
A 60-GHz dual conversion down-converter based on n-type Silicon-based Schottky diodes has been demonstrated in the low-cost 0.18-mu m CMOS technology. Four Schottky diodes in the ring shape configuration with two Marchand Baluns are used for the RF mixer while a double-balanced resistive mixer is used as the second down-converted IF mixer. As a result, the 60-GHz dual-conversion down-converter has conversion gain around 6 dB and noise figure around 18 dB in the RF frequency range of 57 similar to 64 GHz. The total power consumption is 32.8 mW at 2.5 V.
60-GHz Dual-Conversion Down-Converter Using Schottky Diode and Dual-Band Rat-Race Coupler in Standard 0.18-mu m CMOS Process
(2013)
Hsiao, Yu-Chih
;
Meng, Chinchun
;
Wei, Hung-Ju
;
Wang, Ta-Wei
;
Huang, Guo-Wei
A 60 GHz dual-conversion down-converter with a microwave mixer in the first conversion and analog mixers in the second conversion is demonstrated in 0.18-mu m CMOS technology. The first down-converted sub-harmonic mixer consists of a rat-race coupler with the dual-band Chebyshev response and Schottky diodes in anti-parallel configuration. The high cut-off frequency of a Schottky diode helps lowering the conversion loss and noise figure of a microwave mixer. A double balanced resistive mixer is used at the second down-converted mixer. As a result, the conversion gain is about 6 dB in the frequency range of 45 similar to 67 GHz and the IF bandwidth is over 1 GHz. IP1dB is about -5-dBm and IIP3 is about 5-dBm at 45 similar to 67 GHz. The single sideband noise figure is 21 dB at 60 GHz. The total power consumption is 71 mW at 2.5 V.
A Ka-Band pHEMT Regenerative Frequency Divider With Quadrature Outputs
(2011)
Hsiao, Yu-Chih
;
Meng, Chinchun
;
Tsung, Kuan-Chang
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Huang, Guo-Wei
;
電機學院
This paper proposed a Ka-band divide-by-two quadrature-outputs regenerative divider using the 0.15-mu m AlGaAs/InGaAs pseudomorphic high electron mobility transistor (pHEMT) technology. The circuit topology consists of one Marchand balun and two Miller dividers. The input Marchand balun with accurately balanced outputs and symmetrical path routing bring about the precisely quadrature outputs of the divider, while the divider operates up to high frequencies thanks to the high performance of the 0.15-mu m pHEMT technology and a semi-insulating substrate. The divider includes a single side-band (SSB) up-converter to verify the quadrature accuracy of the divider\'s outputs. A 35-dB side-band rejection ratio is achieved. The minimum input sensitivity equals 2.7 dBm. The stable division from 32 to 36 GHz in a fractional bandwidth of 12 % can be obtained. This regenerative frequency divider power consumption is 106 mW. Without the SSB test circuit, the layout size is 1.37 x 1.6 mm(2).
Analysis and Design of Broadband LC-Ladder FET LNAs Using Noise Match Network
(2018-02-01)
Hsiao, Yu-Chih
;
Meng, Chinchun
;
Li, Meng-Che
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電機工程學系
;
Department of Electrical and Computer Engineering
A noise match network for the LC-ladder input network of a broadband inductively source-degenerated common-source (CS) field effect transistor (FET) low-noise amplifier (LNA) is established through noise transformation matrix to derive the noise parameters of a broadband LNA. Analytical formulas for the noise factors of a CS FET LNA with a three-section LC-ladder input network are thus obtained based on the design algorithm of optimal noise and input match developed in this paper. Two 3.7-10.5 GHz two-stage LNAs of the same topology are demonstrated using 0.15-mu m pHEMT technology to validate the design methodology. One LNA has all the fully integrated inductors and the other uses two on-chip inductors replaced by two high-Q bondwire inductors for better noise performance. The measurement results show 11-dB power gain with 2.1-dB noise figure for the LNA with the fully integrated inductors and 11-dB power gain with 1.6-dB noise figure for the LNA with two bondwire inductors, respectively.
Balanced Noise Design of Dual-Band 2.4/5-GHz pHEMT LNAs
(2020-01-01)
Meng, Chinchun
;
Chang, Wei-Ling
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Hsiao, Yu-Chih
;
Li, Meng-Che
;
Chien, Hsin-Yi
This paper presents dual-band 2.4/5-GHz dual-band pHEMT LNAs based on a balanced noise design approach using 0.15 m pHEMT technology. A dual-band LNA has two input match frequencies without simultaneous noise match at these two frequencies especially when the extrinsic loss caused by the inductor is absent. Noise parameters as a function of frequencies for a dual-band FET LNA based on the balanced noise performance are developed. The fully integrated pHEMT LNA achieves power gain of 18 dB at 2.4 GHz and 12 dB at 5 GHz and noise figure about 3 dB at 2.4 GHz and 5 GHz, respectively, at 12.6 mA and 3 V. The pHEMT LNA with a bondwire inductor at input match demonstrates a distinct balanced noise performance.
Broadband CMOS Schottky-Diode Star Mixer Using Coupled-CPW Marchand Dual-Baluns
(2017-05-01)
Hsiao, Yu-Chih
;
Meng, Chinchun
;
Peng, Yong-Hao
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電機工程學系
;
Department of Electrical and Computer Engineering
A broadband CMOS Marchand dual-balun using stacked broadside couplers for low odd-mode impedance with surrounded ground planes for high even-mode impedance is employed to achieve a high coupling coefficient needed for a Marchand dual-balun. The demonstrated Marchand dual-balun using 0.18-mu m CMOS technology is designed at 30-GHz center frequency with an insertion loss of 11.5-and 10-dB input return loss bandwidth of over 120%. The bandwidth of 1-dB amplitude imbalance and 10 degrees phase difference are over 100%. A broadband CMOS Schottky-diode star mixer is implemented with two Marchand dual-baluns at RF and local oscillator (LO) ports. As a result, the Schottky-diode star mixer shows conversion loss of 14 dB, LO-to-RF isolation of 26 dB, LO-to-IF isolation of 45 dB, and RF-to-IF isolation of 42 dB within 27-GHz operating bandwidth, respectively.
Design Optimization of Inductively Source-Degenerated FET LNAs Using Noise Transformation Matrix (Invited Talk)
(2016)
Meng, Chinchun
;
Hsiao, Yu-Chih
;
電機工程學系
;
Department of Electrical and Computer Engineering
Analytical formulas of noise parameters for inductively source-degenerated LNAs in single-/dual-band configurations were derived using noise transformation matrix recently. In the past, the design optimization of a single-band LNA was achieved by solving the noise equation explicitly in a tedious way. However, it is difficult to optimize LNAs of other configurations such as dual-band, multi-band and broadband topologies because it becomes formidable to solve the noise equation explicitly. Our recent research shows that the noise equation of an LNA can be solved implicitly using noise transformation matrix and an insightful design optimization of a dual-band LNA is thus obtained. The paper reviews all the previous work of single-band LNAs done by others in the literature and then concludes with our experimental results of a dual-band LNA with the balanced noise performance.
Design Optimization of Single-/Dual-Band FET LNAs Using Noise Transformation Matrix
(2016-02)
Hsiao, Yu-Chih
;
Meng, Chinchun
;
Yang, Chun
;
電機學院
;
College of Electrical and Computer Engineering
This paper describes the design optimization of single-and dual-band inductively source degenerated field-effect transistor low-noise amplifiers (LNAs) using an analytical formula of noise parameters derived through a noise transformation matrix. The dual-band LNA design can be directly expanded from the single-band LNA design using a noise transformation matrix. The derived noise formulas of LNAs reveal that a simultaneous noise and input match (SNIM) can be obtained at a single frequency for a single-band LNA. For a concurrent dual-band LNA, the simultaneous noise match cannot be achieved at two different operating frequencies and thus a balanced design in noise performance is developed using a noise transformation matrix. This paper demonstrates a 5-GHz single-band and a 2.4/5-GHz concurrent dual-band two-stage single-voltage-supply LNA using 0.15-m depletion-mode pseudomorphic HEMT technology to verify design methodology. The inductively source-degenerated common-source amplifier is applied at the input stage. The 5-GHz common-source common-drain (CS-CD) LNA shows 1.4-dB noise figure (NF) with an SNIM. Moreover, the 2.4/5-GHz CS-CD concurrent dual-band LNA has a balanced noise performance of 2.2-dB NF at 2.4 GHz and 2.0-dB NF at 5 GHz, respectively.
pHEMT Single-Voltage-Supply Direct-Conversion Receiver With a 3-10 GHz LC Ladder LNA
(2019-01-01)
Hsiao, Yu-Chih
;
Meng, Chinchun
;
Wang, Chia-Ling
;
Huang, Guo-Wei
;
電子工程學系及電子研究所
A 3-10 GHz single-voltage-supply pHEMT direct-conversion receiver with a wideband LC-ladder inductively source-degenerated common-source low-noise amplifier is demonstrated in this paper. A wideband LR-CR LO generator is applied to the Gilbert mixers. The measurement results shows 13 similar to 15 dB conversion gain and 6-10 dB noise figure in the 3-10 GHz operating frequency range while the LO power is about 8 dBm and IF=300 MHz. The current consumption of the receiver is 70 mA at 3.3 V supply voltage.