Browsing by Author "Hsieh, Chien-Yu"

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Comparison of 4T and 6T FinFET SRAM Cells for Subthreshold Operation Considering Variability-A Model-Based Approach
(2011-03-01)
Fan, Ming-Long
;
Wu, Yu-Sheng
;
Hu, Vita Pi-Ho
;
Hsieh, Chien-Yu
;
Su, Pin
This paper investigates the cell stability of recently introduced four-transistor (4T) and conventional six-transistor (6T) fin-shaped field-effect transistor static random access memory (SRAM) cells operating in a subthreshold region using an efficient model-based approach to consider the impact of device variations. Compared with the 6T cell, this paper indicates that 4T SRAM cells exhibit a better nominal READ static noise margin (RSNM) because of the reduced READ disturb. For 4T cells, the nearly ideal values of V(write, 0) and V(write, 1) guarantee the positive nominal WRITE static noise margin (WSNM) for selected cells. For half-selected cells on the selected bit line, a sufficient margin is observed between WRITE time (for selected cells) and WRITE disturb (for half-selected cells). Using the established model-based approach, the variability of subthreshold 6T and 4T SRAM cells is assessed with 1000 samples. Our results indicate that the 4T driverless cell with a larger mu RSNM and a slightly worse sigma RSNM shows a comparable mu/sigma ratio in RSNM with the 6T cell. Furthermore, for a given cell area, 4T SRAM cells using relaxed device dimensions with reduced sigma RSNM can outperform the 6T cell. For WRITE operation, 4T SRAM cells exhibit a superior WSNM, whereas the design margin between WRITE time and WRITE disturb needs to be carefully examined to ensure an adequate margin considering device variability.
FinFET SRAM Cell Optimization Considering Temporal Variability due to NBTI/PBTI and Surface Orientation
(2010)
Hu, Vita Pi-Ho
;
Fan, Ming-Long
;
Hsieh, Chien-Yu
;
Su, Pin
;
Chuang, Ching-Te
This paper analyzes the impact of intrinsic process variation and NBTI/PBTI induced time-dependent variations on the stability/variability of 6T FinFET SRAM cells with various surface orientations. Due to quantum confinement, (110)-oriented pull-down devices with fin Line Edge Roughness (LER) show larger Vread,0 and Vtrip variations, thus degrading RSNM and its variability. (100)-oriented pull-up devices with fin LER show larger Vwrite,0 and Vtrip variations, hence degrade the variability of WSNM. The combined effects of intrinsic process variation and NBTI/PBTI induced variations have been examined to optimize the FinFET SRAM cells. Pull-up devices with (110) orientation suffer larger NBTI, resulting in large Vtrip variation and significant degradation of RSNM. Our study indicates that consideration of NBTI/PBTI induced temporal variation changes the optimal choice of FinFET SRAM cell surface orientations in term of mu RSNM/sigma RSNM.
FinFET SRAM Cell Optimization Considering Temporal Variability Due to NBTI/PBTI, Surface Orientation and Various Gate Dielectrics
(2011-03-01)
Hu, Vita Pi-Ho
;
Fan, Ming-Long
;
Hsieh, Chien-Yu
;
Su, Pin
;
Chuang, Ching-Te
This paper analyzes the impacts of intrinsic process variations and negative bias temperature instability (NBTI)/positive BTI (PBTI)-induced time-dependent variations on the stability/variability of 6T FinFET static random access memory (SRAM) cells with various surface orientations and gate dielectrics. Due to quantum confinement, (110)-oriented pull-down n-channel FETs with fin line-edge roughness (LER) show larger Vread, 0 and Vtrip variations, thus degrading READ static noise margin (RSNM) and its variability. Pull-up p-channel FETs with fin LER that are (100)-oriented show larger Vwrite, 0 and Vtrip variations, hence degrade the variability of WRITE SNM. The combined effects of intrinsic process variations and NBTI/PBTI-induced statistical variations have been examined to optimize the FinFET SRAM cells. Worst-case stress scenario for SNM stability/variability is analyzed. With the presence of both NBTI and PBTI in high-k metal-gate FinFET SRAM, the RSNM suffers significant degradation as Vread, 0 increases, whereas Vtrip simultaneously decreases. Variability comparisons for FinFET SRAM cells with different gate stacks (SiO(2) and SiO(2)/HfO(2)) are also examined. Our paper indicates that the consideration of NBTI/PBTI-induced temporal variation changes the optimal choice of FinFET SRAM cell surface orientations in terms of the mu/sigma ratio in RSNM.
Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs
(2012-07-01)
Hsieh, Chien-Yu
;
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Su, Pin
;
Chuang, Ching-Te
In this work, we propose three novel independently-controlled-gate Schmitt Trigger (IG_ST) FinFET SRAM cells for sub-threshold operation. The proposed IG_ST 8 T SRAM cells utilize split-gate FinFET devices with the front-gate devices serving as the stacking devices, and the back-gate devices serving as the intermediate node conditioning devices to provide built-in feedback mechanism for Schmitt Trigger action, thus reducing the cell transistor count/area and achieving improved static noise margin (SNM) and better tolerance to process variation and random variations. 3-D mixed-mode simulations are used to evaluate the Read static noise margin (RSNM), Write static noise margin (WSNM), hold static noise margin (HSNM), and Standby leakage of proposed cells, and results are compared with the standard 6 T cells and previously reported 10 T Schmitt Trigger sub-threshold SRAM cells. Compared with the conventional tied-gate 6 T cell, the proposed IG_ST SRAM cells demonstrate 1.81X and 2.11X higher nominal RSNM at V-CS = 0.4 and 0.15 V, respectively. The cell layouts and areas are assessed based on scaled ground rules from 32 nm node, and the density advantage over previously reported 10 T Schmitt Trigger sub-threshold SRAM cells are illustrated. The cell AC performance (Read access time, Write time, and Read access time versus the number of cells per bit-line considering worst-case data pattern for bit-line leakage) and temperature dependence are evaluated, and shown to be adequate for the intended sub-threshold applications. Compared with previously reported 10 T Schmitt Trigger sub-threshold SRAM cells, the proposed cells exhibit comparable or better RSNM, higher density, and lower Standby leakage current. 3-D mixed-mode Monte Carlo simulations are performed to investigate the impacts of process variations (L-eff, EOT, W-fin, and H-fin) and random variations (Gate LER and Fin LER) on RSNM, WSNM, and HSNM. Our results indicate that even at the worst corner, two of the proposed cells can provide sufficient margin of mu/sigma ratio.
Independently-Controlled-Gate FinFET Schmitt Trigger Sub-threshold SRAMs
(2010)
Hsieh, Chien-Yu
;
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Su, Pin
;
Chuang, Ching-Te
We propose three novel Independently-controlled-Gate Schmitt Trigger (IG_ST) FinFET SRAM cells for sub-threshold operation. The proposed IG ST 8T SRAM cells utilize split-gate FinFET devices to provide built-in feedback mechanism for Schmitt Trigger action. 3D mixed-mode simulations [1] are used to evaluate the RSNM, WSNM, HSNM, and Standby leakage of proposed cells. The proposed cells demonstrate 1.81X and 2.11X higher nominal RSNM at V(CS)=0.4V and 0.15V, respectively. The cell AC performance are evaluated, and shown to be adequate for the intended sub-threshold applications. Compared with previously reported 10T Schmitt Trigger sub-threshold SRAM cells, the proposed cells exhibit comparable or better RSNM, higher density, and lower Standby leakage current. 3D mixed-mode Monte Carlo simulations are performed to investigate the impacts of process variations (L(eff) and W(fin)) and random variations (Gate LER and Fin LER) on RSNM. Our results indicate that even at the worst corner, two of the proposed cells can provide sufficient margin of mu/sigma ratio=7. With enhanced cell stability, reduced cell area and Standby leakage, adequate performance, and robust tolerance to process variations and random variations, these proposed cells are promising candidates for future ultra-low-voltage sub-threshold applications.