Browsing by Author "Hsieh, E. R."

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A Circuit Level Variability Prediction of Basic Logic Gates in Advanced Trigate CMOS Technology
(2014)
Hsieh, E. R.
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Hung, C. M.
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Wang, T. Y.
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Chung, Steve S.
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Huang, R. M.
Variability has been one of the major scaling issues in advancing the CMOS technology. In this paper, a variation model from the device level to circuit level has been proposed and demonstrated on advanced trigate FinFETs. First, a simple and accurate transport model was developed to model variability at the device level. It was then implemented in Spice and the calculation of variation of basic logic gate building block was demonstrated with only W/L and the slopes, A(vt), A(gm), in the Pelgrom plot, as inputs. Finally, a unified simple analytic form was developed to predict the variability of various basic logic circuits regardless of the number of devices and the complexity of circuits.
A Comprehensive Transport Model for High Performance HEMTs Considering the Parasitic Resistance and Capacitance Effects
(2014)
Hung, C. M.
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Li, K. C.
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Hsieh, E. R.
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Wang, C. T.
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Kou, C. I.
HEMT suffers from parasitic resistance (R-sd) and capacitance(C-gd) effects with the shrinking of channel length, leading to degraded performance in logic and RF applications. A new while simple method to extract parasitic RC has been proposed to construct accurate transport parameters in HEMTs. In comparison to the constant-R-sd method, this new voltage dependent method provides more convincing results, especially for very short channel devices. On the other hand, an accurate C-gd correction method has also been incorporated to adequately represent the mobility. Finally, a guideline to design high performance HEMTs has been proposed.
A New and Simple Experimental Approach to Characterizing the Carrier Transport and Reliability of Strained CMOS Devices in the Quasi-Ballistic Regime
(2009)
Hsieh, E. R.
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Chung, Steve S.
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Liu, P. W.
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Chiang, W. T.
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Tsai, C. H.
A new yet simple approach, V(D,sat) method, without complicate temperature measurement setup, has been developed to investigate the carrier transport characteristics for MOSFET devices in the quasi-ballistic regime. It has shown quite good matches with that of Temperature Dependent Method (TDM) developed from the quantum theory [1]. For the first time, the carrier transport properties after HC stress were also examined based on the proposed method. Moreover, method has been applied to examine the carrier transport and reliabilities in advanced strain-CMOS devices. In terms of the device performance, the enhancement of the drain current is strongly related to the transport parameter, the injection velocity, V(inj) which serves as a good monitor for the strain design and current enhancement. While, considering the device reliability after the HC stress, ballistic efficiency, B(sat) is responsible for the I(D) degradation as a result of the increase in interface scatterings. Finally, a roadmap of the V(inj) from those reported results has been provided which serves as a good reference for designing high performance strain-based CMOS devices.
A New Observation of Strain-Induced Slow Traps in Advanced CMOS Technology with Process-Induced Strain Using Random Telegraph Noise Measurement
(2009)
Lin, M. H.
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Hsieh, E. R.
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Chung, Steve S.
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Tsai, C. H.
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Liu, P. W.
In this paper, the hot-carrier induced oxide trap and its correlation with enhanced degradation in strained CMOS devices have been reported for the first time. First, the I(D)-RTN (Drain Current Random Telegraph Noise) has been employed to study the HC stress induced slow oxide traps in strained nMOSFETs and pMOSFETs. Secondly, different behavior of the slow traps in nMOSFET and pMOSFET has been observed. Results show that the vertical compressive strain generates extra oxide defects and induces more scattering after the HC stress in CESL nMOSFET. This vertical strain in CESL, also contributes to a non-negligible amount of extra device degradation. While, SiGe S/D pMOSFET shows different behavior in that the compressive strain in this structure shows no impact on its reliability.
A New Variation Plot to Examine the Interfacial-dipole Induced Work-function Variation in Advanced High-k Metal-gate CMOS Devices
(2016)
Hsieh, E. R.
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Wang, Y. D.
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Chung, Steve S.
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Ke, J. C.
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Yang, C. W.
The interfacial dipole and bulk trap in HKMG stack have been found to be significant to the work function variation (sigma V-WF), in addition to the metal grains. In order to differentiate their effects on sigma V-WF, a new variation plot is proposed and the dipole and trap effects can be distinguished. Here, we propose a simple experimental method to separate the effects of MG/HK and HK/IL interfacial dipoles. In pMOSFET, HK/IL dipoles dominate HK induced variation; MG/HK dipoles are dominant in nMOSFET. However, in terms of the reliability test, after PBTI stress, HK bulk traps play a major role in the variation of nMOSFET, while after NBTI, HK/IL dipoles are strengthened by hydrogen bonds and still dominant in work function variation of pMOSFET. Design guideline is provided to deal with the passivation of high-k traps by nitrogen concentration and the improvement of variability in HKMG CMOS devices.
A Novel Architecture to Build Ideal-linearity Neuromorphic Synapses on a Pure Logic FinFET Platform Featuring 2.5ns PGM-time and 10(12) Endurance
(2019-01-01)
Hsieh, E. R.
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Chang, H. Y.
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Chung, Steve S.
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Chen, T. P.
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Huang, S. A.
In this work, we will explore pure logic FinFET devices to realize the functionality of linear weight tuning capability as electric synapses. The unit cell of this new FinFET synapse is composed of two identical FinFETs in series; one serves as control and the other one as storage. This new FinFET synapse exhibits ideal linearity with nearly infinity training cycles (>10(12)). much lower programming voltage, 0.85V, and faster speed, 2.5ns. It can also analogically increase or decrease the transistor's V-th, to vary the drain conductance. As far as the analog performance is concerned, it performs excellent linearity and a wide tuning-window (20x) of weight-tuning capability. 1kb synaptic array has also been designed. The spice-simulated results have shown that new FinFET synaptic array can expand the array-size to 64x64, exhibiting 300x of SNR, w.r.t. that of RRAM array. Finally, the training of the neural network based on the proposed FinFET synapse can achieve 97.43% accuracy as high as the GPU one does.
A Novel Design of P-N Staggered Face-tunneling TFET Targeting for Low Power and Appropriate Performance Applications
(2017-01-01)
Hsieh, E. R.
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Fan, Y. C.
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Chang, K. Y.
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Liu, C. H.
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Chien, C. H.
A novel complementary tunneling FET (C-TFET) has been designed and targeted for the low power and appropriate performance applications (Apps). In this new architecture of C-TFET, the drain and source (D/S) are configured as a staggered structure to increase the tunneling current, and the conventional p-i-n junction C-TFET has been modified as a p-n junction to further enhance the I-on current. The results show that new design can achieve 310uA/um(n), 440uA/um(p) TFETs of I-on, comparable to those of LP planar CMOS devices, 0.1 nA/um of I-off, while excellent S.S.(<10mV/dec) at V-dd= 0.7V, which will be a promising candidate for the low-power and appropriate performance apps in the next decade.
A Novel One Transistor Non-volatile Memory Feasible for NOR and NAND Applications in IoT Era
(2016)
Chung, Steve S.
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Hsieh, E. R.
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Yang, S. P.
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Chuang, C. H.
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電子工程學系及電子研究所
For the first time, we propose a one transistor nonvolatile memory which can solve the long time charge loss issue incurred in the conventional nitride-storage cell, a hurdle to the scaling of SONOS memory. The SONOS cell uses charge as the storage, while the new invention discloses a cell with one transistor and the gate connected to a simple MIM structure. The readout is from the transistor\'s Vth or I-d, similar to that of flash memory. A bilayer MIM is preferable for best performance. Results demonstrated that this memory exhibits excellent endurance, retention, large window, which can also solve the sneak path and forming issues in conventional crossbar ReRAM. The architecture is fully compatible with the logic CMOS technology and well-suited for both NOR and NAND memories, especially for future embedded applications.
A Novel One Transistor Resistance-Gate Nonvolatile Memory
(2016)
Chung, Steve S.
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Hsieh, E. R.
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Yang, S. P.
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Chuang, C. H.
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電子工程學系及電子研究所
A Novel ReWritable One-Time-Programming OTP (RW-OTP) Realized by Dielectric-fuse RRAM Devices Featuring Ultra-High Reliable Retention and Good Endurance for Embedded Applications
(2018-01-01)
Cheng, H. W.
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Hsieh, E. R.
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Huang, Z. H.
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Chuang, C. H.
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Chen, C. H.
A novel concept of OTP has been demonstrated to create another feasibility to allow re-writable capability before storing the data. This OTP is named ReWritable One-time programming (RW-OTP) memory. With RW-OTP, users can do the test by modifying the contexts repeatedly before finalizing the stored data. To implement the memory cell, it consists of a gate-floated FinFET and an RRAM where a bilayer has been designed as a thicker dielectric layer with resistive-switching property on a thinner dielectric-fuse layer. Moreover, the process of RW-OTP is fully compatible with the state-of-the-art CMOS logic technology. The result shows that the memory cell exhibits high retention and good endurance. With proper use of RW-OTP, the users can not only reduce error jobs cost-efficiently but also can develop various applications for their needs. This memory cell is very promising for embedded applications.
A theoretical and experimental evaluation of surface roughness variation in trigate metal oxide semiconductor field effect transistors
(2016-05-28)
Hsieh, E. R.
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Chung, Steve S.
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A gate current variation measurement method is proposed to examine the surface roughness of metal oxide semiconductor field effect transistors (MOSFETs). This gate current variation is demonstrated on the trigate structure MOSFETs. It was found that the standard deviation of oxide-thickness is proportional to the inverse of square-root of device areas, and its slope is defined as the effective surface roughness variation. In particular, for the transistors with varying fin height, this surface roughness effect aggravates with the increasing fin height. More importantly, the gate leakage at off-state, i.e., Vg = 0V, is strongly dependent on the gate dielectric surface roughness and dominates the drain current variations. This gate leakage may serve as a quality measure of a low power and energy efficient integrated circuit, especially for the transistor with 3-dimensional gate structure. The present results provide us better understandings on an additional source of V-th fluctuations, i.e., the surface roughness variation, in addition to the random dopant fluctuation, that we are usually not noticed. In particular, this study also provides us a simple easy-to-use method for the monitoring of oxide quality in the volume production of trigate MOSFETs. Published by AIP Publishing.
An Energy Efficient FinFET-based Field Programmable Synapse Array (FPSA) Feasible for One-shot Learning on EDGE AI
(2018-01-01)
Kuo, J. L.
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Chen, H. W.
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Hsieh, E. R.
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Chung, Steve S.
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Chen, T. P.
A pure logic 14nm FinFET with capabilities of linearly tunable V-th and excellent retention has been implemented as synapses in neuromorphic system., a Field Programmable Synapse Array (FPSA) has been adopted to replace conventional R-based memory Synapse Array (RSA). Thanks to the wide range of V-t-tuning ability, 200X on/off ratio, and the ultra-small variability, 12%, results showed that the training power and SN ratio of FPSA are 10 times and 50 times smaller than those of the RSA, respectively. Two applications were demonstrated on FPSA array for one-shot learning applications. First, FPSA is used to detect handwritten digits of MNIST dataset. "Learned it by once" can be achieved in this task. Furthermore, FPSA has been applied to recognize goldfish in Cifar 100 dataset after learned the other 4 fish species. With the assistance from one-shot learning, results show the machine learned it faster and better on EDGE. This demonstrates the feasibility of FPSA for low-power and cost-effective synapse-based one-shot learning applications in the AIoT era.
An Innovative 1T1R Dipole Dynamic Random Access Memory (DiRAM) featuring High Speed, Ultra-low power, and Low Voltage Operation
(2016)
Hsieh, E. R.
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Chuang, C. H.
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Chung, Steve S.
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
For the first time, a new 1T1R of volatile memory based on the interfacial dipole flipping mechanism, named as Dipole Dynamic Random Access Memory (DiRAM), has been reported. It features 4ns per bit of dipole switching time, larger than 109 of endurance, and 10 seconds of retention with reasonable positive and negative resistance window, low operation voltages with bit line at 0.8V and word line at 0.2V, and around 1 nano-Watt per bit of operation power. DiRAM is also easy to be integrated with state-of-the-art CMOS technology. The results have shown that this volatile memory may be a potential candidate for the next generation DRAM technology.
Design of Complementary Tilt-gate TFETs with SiGe/Si and III-V Integrations Feasible for Ultra-low-power Applications
(2015)
Hsieh, E. R.
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Lin, Y. S.
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Zhao, Y. B.
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Liu, C. H.
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Chien, C. H.
A new concept of the structure design with an alignment between the maximum band-to-band tunneling rate and electric field has been proposed to enhance the performance of TFETs. It was found that the specific gate of TFET to form an obtuse shape can dramatically improve the on-current of TFET, with over 4 order improvement in comparison to planar ones. This complementary TFET (CTFET) was also demonstrated by SRAM as a benchmark, with SiGe/Si integrated with III-V on Si substrate. In order to increase WNM and RSNM of CTFET SRAM, a new scheme has been adopted, in which SRAM has been successfully demonstrated with operating bias down to 0.3V.
Design of High-Performance and Highly Reliable nMOSFETs with Embedded Si:C S/D Extension Stressor(Si:C S/D-E)
(2009)
Chung, Steve S.
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Hsieh, E. R.
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Liu, P. W.
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Chiang, W. T.
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Tsai, S. H.
A Novel strained nMOSFET with embedded Si:C in S/D extension stressor (Si:C S/D-E) was presented. Comparing to the bulk device, it revealed good drive current ION (+27%), high I(D.sat) current (+67%), enhanced channel mobility (+105%), at a lower effective substitutional carbon concentration (C%-1.1%), using the poly-gate 40nm-node Si:C/eSiGe S/D CMOS technology. Moreover. PBTI effect was first observed in this device as a result of Carbn impurity out-diffusion, which is of critically important for the design trade-off between performance and reliability.
Embedded PUF on 14nm HKMG FinFET Platform: A Novel 2-bit-per-cell OTP-based Memory Feasible for IoT Secuirty Solution in 5G Era
(2019-01-01)
Hsieh, E. R.
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Wang, H. W.
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Liu, C. H.
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Chung, Steve S.
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Chen, T. P.
In this work, a novel concept of 2-bit-per-cell (2B/C) is introduced to realize high-density OTP PUF from a new scheme of dielectric breakdown. This PUF shows 10(5)x of large window, good immunity to high-temperature disturbance, and excellent retention under 150 degrees C baking, which are particularly for automotive applications. In terms of security. this PUF exhibits near ideal normal distribution of hamming distance and narrow distribution of hamming weight. The bit error rates are low, 0.78% at 25 degrees C and 1.95% at 150 degrees C, benchmarked on a 256-bit array. Finally, the security test of this PUF against the hackers' attack from the machine learning process has been proved to have high security. Overall, the proposed 2B/C OTP PUF demonstrated great potential for IoT security in 5G era.
Experimental Techniques on the Understanding of the Charge Loss in a SONOS Nitride-storage Nonvolatile Memory
(2016)
Hsieh, E. R.
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Wang, H. T.
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Chung, Steve S.
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Chang, Wayne
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Wang, S. D.
The endurance and charge loss are the most critical issue in the design of a SONOS memory cell. The origin of the window closure and charge loss was partly caused by the electrons and holes mismatch along the channel lateral direction during the cycling. In this paper, two measurement techniques to observe the mismatch of programmed electrons and erased holes have been developed. It was demonstrated on an MTP (Multi-Time-Programming) SONOS flash memory. By observing the charge distribution, the mismatch which led to window closure and charge loss can be well understood, and better operating schemes can then be developed.
Gate Current Variation: A New Theory and Practice on Investigating the Off-State Leakage of Trigate MOSFETs and the Power Dissipation of SRAM
(2013-01-01)
Hsieh, E. R.
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Lin, S. T.
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Chung, Steve S.
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Huang, R. M.
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Tsai, C. T.
A new gate current variation (sIg) has been proposed for the first time and demonstrated on the trigate devices. It was found that gate current variation can serve as an indicator of the gate sidewall surface roughness. A new theory has then been developed and verified experimentally on trigate devices with various fin heights. Results show that surface roughness increases with the increasing fin height. In addition, hot carrier and NBT stresses have also been performed for trigate CMOS devices. It was found that NBTI exhibits the worst Ig variation. Finally, this theory has been tested on the SRAM to examine the standby power dissipation. Results show that the power dissipation is dominated by the pFET NBTI effect.
Geometric Variation: A Novel Approach to Examine the Surface Roughness and the Line Roughness Effects in Trigate FinFETs
(2017-01-01)
Hsieh, E. R.
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Fan, Y. C.
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Liu, C. H.
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Chung, Steve S.
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Huang, R. M.
A new theory has been developed for geometric variation of trigate FinFETs. This geometric variation includes both line roughness induced variation and oxide-thickness variation, which can be measured from gate capacitance and Ig current variations, respectively. Experimental results show that trigate devices are subject to serious line variations as the fin height scales up and the fin-width scales down, leading to large Ion current variation, i.e., as we increase the fin aspect-ratio, line variation becomes worse which shows an increase of the active power consumption. On the other hand, oxide-thickness variation reveals significant impacts on the off-state leakage, i.e., a rough gate oxide yields to larger static power. These valuable results provide us important guideline for the design and manufacturing of high quality 3D gate FinFETs.
High-Density Multiple Bits-per-Cell 1T4R RRAM Array with Gradual SET/RESET and its Effectiveness for Deep Learning
(2019-01-01)
Hsieh, E. R.
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Giordano, M.
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Hodson, B.
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Levy, A.
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Osekowsky, S. K.
We present the first demonstration of 1T4R Resistive RAM (RRAM) array storing two bits per RRAM cell. Our HfO2-based RRAM is built using a logic foundry technology that is fully compatible with the CMOS back-end process. We present a new approach to program RRAM cells using gradual SET/RESET pulses while minimizing disturbances on adjacent cells (belonging to the same 1T4R RRAM structure) this new approach makes pour multiple-bits-per-cell 1T4R RRAM array demonstration possible. We report over 106 cycles of endurance and a projected 10-year retention at 120 degrees C. Using measured data from our 2 bits-per-cell 1T4R RRAM array, we analyze multiple deep learning applications and demonstrate high degrees of inference accuracy (within 0.01% of ideal values).