Browsing by Author "Hsieh, E. Ray"

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A 14-nm FinFET Logic CMOS Process Compatible RRAM Flash With Excellent Immunity to Sneak Path
(2017-12-01)
Hsieh, E. Ray
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Kuo, Yen Chen
;
Cheng, Chih-Hung
;
Kuo, Jing Ling
;
Jiang, Meng-Ru
In this paper, we have demonstrated an oxygen-vacancy-based bipolar RRAM on a pure logic 14-nm-node HKMG FinFET platform. A unit cell of the memory consists of a control transistor (FinFET) and a storage transistor (a second FinFET). The later performs as a bipolar RRAM. This unit cell can be integrated in an AND-type memory array. The memory cell has an ON/OFF ratio equal to 200 and 400 for the n-type and p-type FinFET RRAMs, respectively, endurance larger than 400 and 1000 times for n- and p-type devices, respectively, and the retention test for over 1 month under 125 degrees C temperature environment. To analyze the array performance of the AND-type FinFET RRAM at the circuit level, we have further discussed the issues of the sneak path and disturbance, in which an active-fin isolation of FinFET in an AND-type array has been suggested to minimize the leakage current induced by sneak paths. The results have shown a large window with up to 103 ON/OFF ratio, 30% standby power reduction, and 90% active power reduction with reference to the conventional AND-type array. As a result, the bipolar FinFET RRAM exhibits great potential for the embedded memory applications, in particular it can be extended to 28-nm HKMG and the FinFET platform beyond 14-nm technology node, to fill the Moore's gap between the high-performance logic and the embedded memory.
An Experimental Approach to Characterizing the Channel Local Temperature Induced by Self-Heating Effect in FinFET
(2018-01-01)
Hsieh, E. Ray
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Jiang, Meng-Ru
;
Lin, Jian-Li
;
Chung, Steve S.
;
Chen, Tse Pu
In this paper, we have developed a methodology of a lateral profiling technique of the channel local temperature in 14 nm FinFET, incurred by the self-heating effect (SHE). As SHE happens, the thermal source generated near the drain will dissipate toward the source side. Since the interaction between RTN trap and channel carriers is very sensitive to the temperature, the channel local temperature can be extracted through this interaction process between random-telegraph-noise (RTN) trap and carriers, and the position of the channel local temperature can be obtained from the RTN trap position. The results show that the highest temperature happens at the drain edge during SHE and pFinFET exhibits a much higher temperature than that of nFinFET. Furthermore, the distribution of channel local temperature can be described by the Fourier's law of thermal conduction. Averaged channel temperature can be used to extract the thermal resistance, R-th, which increases rapidly as the channel length is scaled down to 20 nm, further degrading the SHE, in terms of a significant short channel effect. We also found that the incremental channel resistance is proportional to the incremental channel local temperature, whose slope indicates the degree of SHE, and the slope of pFinFET is larger than that of nFinFET. Finally, SHE will cause 10% and 14% degradation of IdVds for n- and pFinFET respectively. This can be reasonably explained by the decay of saturation velocity in high temperature. The results obtained based on this methodology will help us on the understanding of the SHE impact on a nano-scaled FinFET device.
The Impact of TiN Barrier on the NBTI in an Advanced High-k Metal-gate p-channel MOSFET
(2017-01-01)
Huang, D. -C.
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Hsieh, E. Ray
;
Gong, J.
;
Huang, C. -F.
;
Chung, Steve S.
This study investigates the bias temperature instability in high-k/metal-gate pMOSFETs with a TiN barrier layer sandwiched between the metal gate electrode and HfO2 dielectric and for reliability improvement of such devices. The experimental results clearly demonstrated that the diffusion mechanism of oxygen and nitrogen resulting from the post metallization treatment was the root cause of bias temperature instabilities in the p-channel MOSFETs. However, the device NBTI reliability is dependent on the nitrogen diffusion from the TiN layer, which degrades the SiO2/Si interfacial layer quality. Results show that by increasing the thickness of TiN barrier layer, the driving current will make worse the NBTI in p-MOSFET. Therefore, optimization needs to be considered for TiN as a barrier to improve the device reliabilities.