Browsing by Author "Hsieh, Jin-Long"
Now showing 1 - 2 of 2
- Results Per Page
- Sort Options
Item type:Item, Enabling n-type polycrystalline Ge junctionless FinFET of low thermal budget by in situ doping of channel and visible pulsed laser annealing(2017-02) ;Huang, Wen-Hsien ;Shieh, Jia-Min ;Kao, Ming-Hsuan ;Shen, Chang-HongHuang, Tzu-EnA low-thermal-budget n-type polycrystalline Ge (poly-Ge) channel that was prepared by plasma in-situ-doped nanocrystalline Ge (nc-Ge) and visible pulsed laser annealing exhibits a high electrically active concentration of 2 x 10(19) cm(-3) and a narrow Raman FWHM of 3.9 cm(-1). Furthermore, the fabricated n-type poly-Ge junctionless FinFET (JL-FinFET) shows an I-on/I-off ratio of 6 x 10(4), V-th of % -0.3 V, and a subthreshold swing of 237mV/dec at V-d of 1V and DIBL of 101mV/V. The poly-Ge JL-FinFET with a high-aspect-ratio fin channel is less sensitive to V-th roll-off and subthreshold-swing degradation as the gate length is scaled down to 50 nm. This low-thermal-budget JL-FinFET can be integrated into three-dimensional sequential-layer integration and flexible electronics. (C) 2017 The Japan Society of Applied PhysicsItem type:Item, Junction-less poly-Ge FinFET and charge-trap NVM fabricated by laser-enabled low thermal budget processes(2016-06-13) ;Huang, Wen-Hsien ;Shieh, Jia-Min ;Shen, Chang-Hong ;Huang, Tzu-EnWang, Hsing-HsiangA doping-free poly-Ge film as channel material was implemented by CVD-deposited nano-crystalline Ge and visible-light laser crystallization, which behaves as a p-type semiconductor, exhibiting holes concentration of 1.8 x 10(18) cm(-3) and high crystallinity (Raman FWHM similar to 4.54 cm(-1)). The fabricated junctionless 7 nm-poly-Ge FinFET performs at an I-on/I-off ratio over 10(5) and drain-induced barrier lowering of 168mV/ V. Moreover, the fast programming speed of 100 mu s-1 ms and reliable retention can be obtained from the junctionless poly-Ge nonvolatile-memory. Such junctionless poly-Ge devices with low thermal budget are compatible with the conventional CMOS technology and are favorable for 3D sequential-layer integration and flexible electronics. Published by AIP Publishing.