Browsing by Author "Hsieh, Kuang-Yeu"

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A 2-bit/cell, maskless, self-aligned resistance memory with high thermal stability
(2007)
He, ChiaHua
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Lee, Ming-Daou
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Pan, Chen-Ling
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Lai, Erb-Kun
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Yao, Yeong-Der
We report the first demonstration of a multilevel cell (MLC) resistance device using a self-aligned WO, film prepared by plasma oxidation. The 2-bit/cell operation is achieved by applying a series of 1.5V programming pulses. The device shows high thermal stability and good data retention. The resistance change can be attributed to variable-range hopping and Ohmic transport mechanisms. This device has the potential for future low-voltage, 3-dimentioanl nonvolatile memory with multiple bits per layer. In addition, no additional mask is needed to form the self-aligned device.
A Study of Blocking and Tunnel Oxide Engineering on Double-Trapping (DT) BE-SONOS Performance
(2015)
Lo, Roger
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Du, Pei-Ying
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Hsu, Tzu-Hsuan
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Wu, Chen-Jun
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Guo, Jung-Yi
Double-trapping bandgap engineered SONOS (DT BE-SONOS) [1] was proposed to provide both fast erase speed and deep erase by means of a second nitride trapping layer and an additional blocking oxide on top of BE-SONOS. Although this provides excellent erase performance but the additional layers increase the EOT and subsequently the erase voltage, thus it is desirable to minimize their impact. This work investigates exhaustively the effect of thinning down the blocking layers. Since the ISPP and high temperature retention charge loss are mainly dominated by the ONO thickness of BE-SONOS below the blocking layers, reducing the blocking layer thickness has only minor impact on ISPP and retention. Moreover, erase saturation is determined by the dynamic balance of channel hole injection and gate electron injection. Experimental data show that reducing the thickness of the oxide between two trapping layers has little impact on erase saturation once the gate injected electrons are efficiently suppressed by the top most oxide. We have also investigated retention improvement by various oxides. By using HQ-SiO2 to replace the top tunnel ONO the trapped electron out-tunneling is reduced. Thus retention may be improved without increasing the effective oxide thickness.
A study of gate-sensing and channel-sensing (GSCS) transient analysis method - Part II: Study of the intra-nitride behaviors and reliability of SONOS-type devices
(2008-08-01)
Du, Pei-Ying
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Lue, Hang-Ting
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Wang, Szu-Yu
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Huang, Tiao-Yuan
;
Hsieh, Kuang-Yeu
For the first time, we can directly investigate the charge transport and intra-nitride behaviors of SONOS-type devices by exploiting the gate-sensing and channel-sensing (GSCS) method. Our results clearly indicate that for electron injection (+FN program), the electron centroid migrates from the bottom toward the nitride center, whereas for hole injection (-FN erase), holes first recombine with the bottom electrons and then gradually move upward. For the electron de-trapping processes under -V(G) stressing, the trapped electrons de-trap first from the bottom portion of nitride. We also develop a method to distinguish the electron de-trapping and hole injection erasing methods by comparing the erasing current density (J) versus the bottom oxide electric field (E). At short-term high-temperature baking, the electrons move from the top portion toward the bottom portion, and this intra-nitride transport becomes more significant for a thicker nitride. On the other hand, after long-term baking, the charge loss mainly comes from the bottom portion of nitride.
Excellent Resistance Variability Control of WOx ReRAM by a Smart Writing Algorithm
(2016)
Lin, Yu-Hsuan
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Wu, Jau-Yi
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Lee, Ming-Hsiu
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Wang, Tien-Yen
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Lin, Yu-Yu
TMO ReRAMs, being built on defect states, are intrinsically subject to variability. In this work, cell to cell variability is studied by applying write shots with different current and voltage for Forming, SET and RESET operation, respectively. We found the keys to eliminate tail bits consist of (1) longer write pulse, (2) higher write current and (3) higher write voltage. In order to optimize the performance of write speed, write power and device reliability, we developed a novel resistance control method using a smart writing algorithm. Compared to the conventional ISPP writing scheme, this smart writing algorithm covers much wider switching condition variability and cell-to-cell variation by controlling both current and voltage for ReRAM operation.
Highly reliable MA BE-SONOS (Metal-Al2O3 bandgap engineered SONOS) using a SiO2 buffer layer
(2008)
Lai, Sheng-Chih
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Lue, Hang-Ting
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Liao, Chien-Wei
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Wu, Tai-Bor
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Yang, Ming-Jui
A Metal-high-K Bandgap-Engineered SONOS (MA BE-SONOS) with an additional SiO2 buffer layer is proposed. The thin SiO2 (5 similar to 6 nm) layer between the high-K (Al2O3) and nitride serves to prevent shallow trap generation. Contrary to the previously proposed MANOS or MA BE-SONOS devices using a simple high-k top dielectric, this composite structure eliminates the unstable high-K/nitride interface. Experimental results show that this new device can well suppress the erase saturation, just like MANOS. On the other hand, the data retention is greatly improved, owing to the much more stable interface between the nitride-trapping layer and top oxide. Very large memory window (> 7V) with excellent cycling endurance, read disturb immunity, and data retention has been successfully demonstrated. Theoretical model is also proposed to explain the principle of this device.
Impact of V-pass Interference on Charge-Trapping NAND Flash Memory Devices
(2015-06-01)
Hsiao, Yi-Hsuan
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Lue, Hang-Ting
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Chen, Wei-Chen
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Chang, Kuo-Pin
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Tsui, Bing-Yue
The impact of adjacent word-line\'s pass gate voltage interference on charge-trapping (CT) NAND Flash is extensively studied in this paper. From our previous work with a 38-nm half-pitch BE-SONOS NAND Flash device, we found that the threshold voltage significantly decreases with increasing pass gate voltage during reading. This observation is in contrary to the common belief that the CT NAND devices are immune to interference. In this paper, we further evaluate the pass gate voltage interference on 3-D CT NAND Flash, which is the most promising path for the future NAND Flash industry. Owing to the superior gate control ability in the double-gate architecture, the commonly observed pass gate voltage interference due to pitch scaling is suppressed. Stronger gate control ability also restrains the impact of field penetration in devices with narrow channel width. In 3-D CT NAND Flash, the thinner channel can also provide better gate control ability, which, in turn, results in smaller pass gate voltage interference.
Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D NAND Flash Memory Devices
(2014-06-01)
Hsiao, Yi-Hsuan
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Lue, Hang-Ting
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Chen, Wei-Chen
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Chang, Kuo-Pin
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Shih, Yen-Hao
The 3-D stacking of multiple layers of NAND using thin-film transistor (TFT) devices is widely accepted as the next step in continuing NAND Flash scaling. Low mobility and reliability problems are two well-known concerns regarding TFT devices. However, another important implication of using TFT devices is that the Vt variation induced by randomly distributed grain boundaries degrades the array performance. In this paper, an extensive TCAD simulation was conducted to systematically investigate how grain boundary generated traps affect NAND Flash devices. Minimizing the density of grain boundary traps is crucial for array performance. In addition, optimal gate control ability reduces the impact of grain boundaries. Thus, using double gate architecture in vertical gate 3-D NAND is favorable. Furthermore, when pitch is scaled in the future, device exhibiting smaller channel thickness should be used to increase the gate control.
Pulse-IV Characterization of Charge-Transient Behavior of SONOS-Type Devices With or Without a Thin Tunnel Oxide
(2009-04-01)
Du, Pei-Ying
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Lue, Hang-Ting
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Wang, Szu-Yu
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Huang, Tiaci-Yuan
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Hsieh, Kuang-Yeu
The transient behavior of SONOS-type devices was investigated for the first time using pulse-IV technique. Three kinds of SONOS devices are studied: SONS (without top oxide), SONoS (with a thin top oxide), and SoNOS (with a thin bottom oxide). Devices with or without a thin tunnel oxide were able to provide very fast charge injection/detrapping, but their charge-transient behavior cannot be accurately monitored by conventional DC-IV method. By using specific pulse-IV setup for memory, we can measure the drain current response immediately after programming and erasing, as well as the fast charge relaxation under various reliability tests. The program and erase transient behavior shows that all devices are easily programmed and erased within 1 mu s at low gate voltages (< 6 V). Moreover, SONS shows the fastest program and erase speeds because of the absence of tunnel oxide, and silicon nitride has very low barrier height that offers fast injection. We have also examined the charge relaxation under various field and temperature conditions and found that the charge loss mainly came from external charge injection during retention, not from detrapping through thermionic emission.
Reliability Study of MANOS with and without a SiO2 Buffer Layer and BE-MANOS Charge-Trapping NAND Flash Devices
(2009)
Liao, Chien-Wei
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Lai, Sheng-Chih
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Lue, Hang-Ting
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Yang, Ming-Jui
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Shen, Chin-Yen
The reliability of MANOS devices with an oxide buffer layer (MAONOS) in between SiN trapping layer and high-K Al2O3 top dielectric is extensively studied. We conclude that the primary function of high-K Al2O3 is to suppress the gate electron injection during erase instead of increasing the P/E speed. As a result, inserting a buffer oxide only changes EOT but does not change the P/E mechanisms. On the other hand, the buffer oxide can greatly improve data retention by suppressing leakage through Al2O3. However, owing to the slow erase performances with a thick bottom oxide, both MANOS and MAONOS erase slowly and very high erase voltages must be used. Also, both MANOS and MAONOS devices show very fast endurance degradation below P/E<10, which is inherent due to electron de-trapping mechanism. Moreover, the large erase voltage also causes severe degradation of tunnel oxide after many P/E cycling. To get both speed and reliability performances, it is necessary to introduce bandgap engineered tunneling barrier (BE-MANOS) to solve the fundamental problems of MANOS.
STUDY OF GATE-INJECTION OPERATED SONOS-TYPE DEVICES USING THE GATE-SENSING AND CHANNEL-SENSING (GSCS) METHOD
(2009)
Du, Pei-Ying
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Lue, Hang-Ting
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Wang, Szu-Yu
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Huang, Tiao-Yuan
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Hsieh, Kuang-Yeu
SONOS devices using gate injection programming and erasing have better cycling endurance because the gate oxide is not stressed by PIE operations. This work studies the gate injection behavior in detail using the recently developed gate-sensing and channel-sensing (GSCS) technique. GSCS accurately locates the charge centroid during programming/erasing and reliability tests. For the first time, we can track the charge centroid for gate-injection "top BE-SONOS" and various SONOS-type devices. Our results indicate that the charge centroid after electron gate injection is close to the nitride center, irrespective of various nitride thickness and top dielectric. Moreover, there is electron and hole vertical mismatch after hole gate injection. Comparing the results from SONS, we can clearly prove that electrons are mainly distributed inside the bulk nitride instead of the interfaces between oxide and nitride. For SNOS and SNS, where there is electron and hole injection simultaneously, two-region approximation can give us more detailed information about electron and hole capture. By comparing experimental data with theoretical modeling, we have shown that nitride 7nm or thicker captures all the injected electrons up to total charge area density similar to 10(13)cm(-2).
Study of the gate-sensing and channel-sensing transient analysis method for monitoring the charge vertical location of SONOS-type devices
(2007-09-01)
Du, Pei-Ying
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Lue, Hang-Ting
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Wang, Szu-Yu
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Lai, Erh-Kun
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Huang, Tiao-Yuan
The gate-sensing and channel-sensing transient analysis method is studied in detail. This method introduces an additional gate-sensing capacitor to be compared with the conventional channel-sensing one. Sensing in both modes provides two equations that are suitable to solve for two variables-the charge density (Q) and the average charge vertical location (x). In this paper, the principle of this method is discussed in detail. Several factors that affect the measurement accuracy are also analyzed. The power of this method is demonstrated by program/erase cycling and data retention tests. This method is indeed a powerful tool for detailed understanding of trapping dynamics.
Tungsten Oxide Resistive Memory Using Rapid Thermal Oxidation of Tungsten Plugs
(2010)
Lai, Erh-Kun
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Chien, Wei-Chih
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Chen, Yi-Chou
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Hong, Tian-Jue
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Lin, Yu-Yu
A complementary metal oxide semiconductor (CMOS)-compatible WO(x) based resistive memory has been developed. The WO(x) memory layer is made from rapid thermal oxidation of W plugs. The device performs excellent electrical properties. The switching speed is extremely fast (similar to 2 ns) and the programming voltage (< 1: 4 V) is low. For single-level cell (SLC) operation, the device shows a large resistance window, and 10(8)-cycle endurance. For multi-level cell (MLC) operation, it demonstrates 2-bit/cell storage with the endurance up to 10000 times. The rapid thermal oxidation (RTO) WO(x) resistance random access memory (RRAM) is very promising for both high-density and embedded memory applications. (C) 2010 The Japan Society of Applied Physics
Ultra-High Bit Density 3D NAND Flash-Featuring-Assisted Gate Operation
(2015-10-01)
Hsiao, Yi-Hsuan
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Lue, Hang-Ting
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Chen, Wei-Chen
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Tsui, Bing-Yue
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Hsieh, Kuang-Yeu
Lower saturation current flowing through the same cell twice is a major drawback of vertical stack array transistor architecture. A loading effect further reduces the saturation current and causes higher threshold voltage. A simple word line cut process not only doubles the bit density to reduce the bit cost, but also reduces the loading effect. This letter used an assisted gate can to further enhance the saturation current with acceptable cell characteristics. Furthermore, the major parameters that influence the performance of the vertical stack array transistor architecture were studied extensively. An ultra-high density three-dimensional NAND flash architecture can be used in the future NAND flash industry.