Browsing by Author "Hsieh, Ting-En"

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AlGaN/GaN MIS-HEMTs With High Quality ALD-Al2O3 Gate Dielectric Using Water and Remote Oxygen Plasma As Oxidants
(2018-12-01)
Wang, Huan-Chung
;
Hsieh, Ting-En
;
Lin, Yueh-Chin
;
Luc, Quang Ho
;
Liu, Shih-Chien
We demonstrate the electrical performances of AlGaN/GaN metal-insulator-semiconductor-high electron mobility transistors (MIS-HEMTs) with high quality Al2O3 gate dielectric deposited by plasma enhanced atomic layer deposition using both H2O and remote O-2 plasma as oxygen sources. Excellent gate-dielectric/GaN interface and Al2O3 film quality were obtained, resulting in a very small threshold voltage hysteresis and a low interface trap density. The MIS-HEMT device exhibited high on/off current ratio of similar to 10(10), steep subthreshold slope, small gate leakage current, low dynamic on-resistance degradation, and effectively current collapse suppression. These results indicate that incorporating remote O-2 plasma in the ALD-Al2O3 deposition process is an effective and simple way to provide high quality gate dielectric for the GaN MIS-HEMTs production.
Au-Free GaN High-Electron-Mobility Transistor with Ti/Al/W Ohmic and WN (X) Schottky Metal Structures for High-Power Applications
(2016-07)
Hsieh, Ting-En
;
Lin, Yueh-Chin
;
Chu, Chung-Ming
;
Chuang, Yu-Lin
;
Huang, Yu-Xiang
In this study, an Au-free AlGaN/GaN high-electron-mobility transistor (HEMT) with Ti/Al/W ohmic and WNx Schottky metal structures is fabricated and characterized. The device exhibits smooth surface morphology after metallization and shows excellent direct-current (DC) characteristics. The device also demonstrates better performance than the conventional HEMTs under high voltage stress. Furthermore, the Au-free AlGaN/GaN HEMT shows stable device performance after annealing at 400A degrees C. Thus, the Ti/Al/W ohmic and WN (X) Schottky metals can be applied in the manufacturing of GaN HEMT to replace the Au based contacts to reduce the manufacturing costs of the GaN HEMT devices with comparable device performance.
Bias- and Temperature-Assisted Trapping/De-trapping of R-ON Degradation in D-mode AlGaN/GaN MIS-HEMTs on a Si substrate
(2017-01-01)
Zhang, Jin-Ming
;
Hsieh, Ting-En
;
Wu, Tian-Li
;
Chen, Szu-Hao
;
Chen, Shi-Xuan
In this study, we investigate the R-ON degradation in D-mode AlGaN/GaN MIS-HEMTs on a Si substrate via an accelerated step stress at different temperatures. We have observed a three-phase R-ON degradation behavior, which is highly correlated with a drain bias and back gate bias. First, the R-ON degradation increases till a peak value when the drain bias increases. Second, when the drain bias increases further, the R-ON degradation is reduced. Third, the R-ON degradation slowly increases again. R-ON degradation is characterized with different temperatures, the results show that 1) high temperature leads to a smaller R-ON degradation compared to the result at room temperature and 2) high temperature shifts the peak of the R-ON degradation at a lower drain bias. A possible mechanism that the trapping and de-trapping could occur due to the high temperature and high drain bias is proposed to explain the observed results.
Comprehensive dynamic on-resistance assessments in GaN-on-Si MIS-HEMTs for power switching applications
(2018-05-01)
Chou, Po-Chien
;
Hsieh, Ting-En
;
Cheng, Stone
;
del Alamo, Jesus A.
;
Chang, Edward Yi
This study comprehensively analyzed the reliability of trapping and hot-electron effects responsible for the dynamic on-resistance (Ron) of GaN-based metal-insulator-semiconductor high electron mobility transistors. Specifically, this study performed the following analyses. First, we developed the on-the-fly Ron measurement to analyze the effects of traps during stress. With this technique, the faster one (with a pulse period of 20 ms) can characterize the degradation; the transient behavior could be monitored accurately by such short measurement pulse. Then, dynamic Ron transients were investigated under different bias conditions, including combined off state stress conditions, back-gating stress conditions, and semi-on stress conditions, in separate investigations of surface-and buffer-, and hot-electron-related trapping effects. Finally, the experiments showed that the Ron increase in semi-on state is significantly correlated with the high drain voltage and relatively high current levels (compared with the off-state current), involving the injection of greater amount of hot electrons from the channel into the AlGaN/insulator interface and the GaN buffer. These findings provide a path for device engineering to clarify the possible origins for electron traps and to accelerate the development of emerging GaN technologies.
Effect of high voltage stress on the DC performance of the Al2O3/AlN GaN metal-insulator-semiconductor high-electron mobility transistor for power applications
(2015-10-01)
Hsieh, Ting-En
;
Lin, Yueh-Chin
;
Liao, Jen-Ting
;
Lan, Wei-Cheng
;
Chin, Ping-Chieh
We demonstrate an Al2O3/AlN/AlGaN/GaN metal-insulator-semiconductor high-electron mobility transistor (MIS-HEMT) device with stable electrical properties under high-voltage stress, by using an Al2O3/AlN stack layer as the gate dielectric layer. Excellent quality AlN/Al2O3 GaN interface was obtained by using plasma-enhanced ALD (PE-ALD), resulting in a very low interface trap density (D-it) of similar to 1.8 x 10(11) eV(-1) cm(-2), obtained by using the conductance method. The device exhibits a small threshold voltage hysteresis of similar to 200 mV and a lower gate-source leakage current. No obvious changes in the drain-source current and ON-resistance were observed for the device that was subject to the drain-source voltage stress of 100 V for 15 h. (C) 2015 The Japan Society of Applied Physics
Evaluation and Reliability Assessment of GaN-on-Si MIS-HEMT for Power Switching Applications
(2017-02-01)
Chou, Po-Chien
;
Chen, Szu-Hao
;
Hsieh, Ting-En
;
Cheng, Stone
;
del Alamo, Jesus A.
This paper reports an extensive analysis of the physical mechanisms responsible for the failure of GaN-based metal-insulator-semiconductor (MIS) high electron mobility transistors (HEMTs). When stressed under high applied electric fields, the traps at the dielectric/III-N barrier interface and inside the III-N barrier cause an increase in dynamic on-resistance and a shift of threshold voltage, which might affect the long term stability of these devices. More detailed investigations are needed to identify epitaxy- or process-related degradation mechanisms and to understand their impact on electrical properties. The present paper proposes a suitable methodology to characterize the degradation and failure mechanisms of GaN MIS-HEMTs subjected to stress under various off-state conditions. There are three major stress conditions that include: V-DS = 0 V, off, and off (cascode-connection) states. Changes of direct current (DC) figures of merit in voltage step-stress experiments are measured, statistics are studied, and correlations are investigated. Hot electron stress produces permanent change which can be attributed to charge trapping phenomena and the generation of deep levels or interface states. The simultaneous generation of interface (and/or bulk) and buffer traps can account for the observed degradation modes and mechanisms. These findings provide several critical characteristics to evaluate the electrical reliability of GaN MIS-HEMTs which are borne out by step-stress experiments.
GaN High-Electron-Mobility Transistor with WNx/Cu Gate for High-Power Applications
(2015-12-01)
Hsieh, Ting-En
;
Lin, Yueh-Chin
;
Li, Fang-Ming
;
Shi, Wang-Cheng
;
Huang, Yu-Xiang
A GaN high-electron-mobility transistor (HEMT) with WN (x) /Cu gate for high-power applications has been investigated. The direct-current (DC) characteristics of the device are comparable to those of conventional Ni/Au-gated GaN HEMTs. The results of high-voltage stress testing indicate that the device is stable after application of 200 V stress for 42 h. The WN (x) /Cu-gated GaN HEMT exhibited no obvious changes in the DC characteristics or Schottky barrier height before and after annealing at 250A degrees C for 1 h. These results demonstrate that the WN (x) /Cu gate structure can be used in a GaN HEMT for high-power applications with good thermal stability.
GaN MIS-HEMTs With Nitrogen Passivation for Power Device Applications
(2014-10-01)
Liu, Shih-Chien
;
Chen, Bo-Yuan
;
Lin, Yueh-Chin
;
Hsieh, Ting-En
;
Wang, Huan-Chung
A GaN MIS-HEMT with nitrogen (N)-passivation for power device applications is demonstrated. In this letter, nitrogen radicals were adopted to recover nitrogen-vacancy-related defects which were formed due to the thermal decomposition and evaporation of nitrogen atoms from GaN surface during high-temperature process. Besides, nitrogen radicals can also remove impurities and reduce surface dangling bonds by forming Ga-N bonds on the SiN/GaN interface. With N-passivation, the device shows high ON/OFF current ratio, steep subthreshold slope, low OFF-state leakage current, high breakdown voltage, and improved dynamic ON-resistance. The device reliability under high-electric field stress was also improved as a result.
Gate Recessed Quasi-Normally OFF Al2O3/AlGaN/GaN MIS-HEMT With Low Threshold Voltage Hysteresis Using PEALD AlN Interfacial Passivation Layer
(2014-07-01)
Hsieh, Ting-En
;
Chang, Edward Yi
;
Song, Yi-Zuo
;
Lin, Yueh-Chin
;
Wang, Huan-Chung
In this letter, a gate recessed normally OFF AlGaN/GaN MIS-HEMT with low threshold voltage hysteresis using Al2O3/AlN stack gate insulator is presented. The trapping effect of Al2O3/GaN interface was effectively reduced with the insertion of 2-nm AlN thin interfacial passivation layer grown by plasma enhanced atomic layer deposition. The device exhibits a threshold voltage of +1.5 V, with current density of 420 mA/mm, an OFF-state breakdown voltage of 600 V, and high ON/OFF drain current ratio of similar to 10(9).
Gate Recessed Quasi-Normally OFF Al2O3/AlGaN/GaN MIS-HEMT With Low Threshold Voltage Hysteresis Using PEALD AlN Interfacial Passivation Layer
(2014-07-01)
Hsieh, Ting-En
;
Chang, Edward Yi
;
Song, Yi-Zuo
;
Lin, Yueh-Chin
;
Wang, Huan-Chung
In this letter, a gate recessed normally OFF AlGaN/GaN MIS-HEMT with low threshold voltage hysteresis using Al2O3/AlN stack gate insulator is presented. The trapping effect of Al2O3/GaN interface was effectively reduced with the insertion of 2-nm AlN thin interfacial passivation layer grown by plasma enhanced atomic layer deposition. The device exhibits a threshold voltage of +1.5 V, with current density of 420 mA/mm, an OFF-state breakdown voltage of 600 V, and high ON/OFF drain current ratio of similar to 10(9).
Halbleitervorrichtung und Verfahren zur Herstellung derselben
(2018-06-21)
CHANG EDWARD YI
;
LIU SHIH-CHIEN
;
HUANG CHUNG-KAI
;
WU CHIA-HSUN
;
HAN PING-CHENG
A semiconductor device includes a substrate, a channel layer, a barrier layer, a recess, a charge trapping layer, a ferroelectric material layer, a gate, a source and a drain. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The barrier layer has a recess, and a portion of the barrier layer under the recess has a thickness. The source and the drain are disposed on the barrier layer. The charge trapping layer covers the bottom of the recess. The ferroelectric material is disposed on the charge trapping layer. The gate is disposed on the ferroelectric material.
High-Performance LPCVD-SiNx/InAlGaN/GaN MIS-HEMTs With 850-V 0.98-m Omega.cm(2) for Power Device Applications
(2018-01-01)
Wang, Huan-Chung
;
Lumbantoruan, Franky Juanda
;
Hsieh, Ting-En
;
Wu, Chia-Hsun
;
Lin, Yueh-Chin
We demonstrate the electrical performances of the quaternary InAlGaN/GaN MIS-HEMTs with high quality SiNx gate dielectric and surface passivation layer deposited by low pressure chemical vapor deposition (LPCVD) at 780 degrees C. Excellent LPCVD-SiNx/InAlGaN interface and SiNx film quality were obtained, resulting in very high output current density, a very small threshold voltage hysteresis and steep subthreshold slope. The LPCVD-SiNx/InAlGaN/GaN MIS-HEMT device exhibited high on/off current ratio, large gate voltage swing, high breakdown voltage, and very low dynamic on-resistance (R-ON) degradation, meaning effective current collapse suppression compared to the plasma enhanced chemical vapor deposition -SiN x /InAlGaN/GaN MIS-HEMTs. The corresponding specific on-resistance (RoN, sp ) for LPCVD-SiN x device was as low as 0.98 m Omega.cm(2), yielding a high figure of merit of 737 MW/cm(2) . These results demonstrate a great potential of the LPCVD-SiNx /InAlGaN/GaN MIS-HEMTs for high-power switching applications.
High-Performance Normally-OFF GaN MIS-HEMTs Using Hybrid Ferroelectric Charge Trap Gate Stack (FEG-HEMT) for Power Device Applications
(2018-07-01)
Wu, Chia-Hsun
;
Han, Ping-Cheng
;
Liu, Shih-Chien
;
Hsieh, Ting-En
;
Lumbantoruan, Franky Juanda
A GaN metal-insulator-semiconductor-high electron mobility transistor (HEMT) using hybrid ferroelectric charge trap gate stack (FEG-HEMT) is demonstrated for normally-OFF operation. The ferroelectric (FE) polarization increases the number of trapped charges in the HfON charge trapping layer, leading to high positive threshold voltage (V-th) shift for the normally-OFF device. Besides, under the positive bias temperature instability (PBTI) test, the internal electric field induced by FE polarization causes smoother slope of the conduction band in FE gate stack, resulting in better V-th stability. With the proposed hybrid FE charge trap gate stack, the device exhibits a high V-th of +2.71 V at I-DS = 1 mu A/mm, a high maximum current density of 820 mA/mm and low on-resistance (R-ON) of 11.1 Omega . mm. The FE device also shows good V-th-temperature stability compared to the non-FE device results. Besides, a high current device with 40 A is also fabricated in this letter to demonstrate the feasibility of the proposed FEG-HEMT device for high power device application.
Normally-OFF GaN MIS-HEMT With F- Doped Gate Insulator Using Standard Ion Implantation
(2018-01-01)
Wu, Chia-Hsun
;
Han, Ping-Cheng
;
Quang Ho Luc
;
Hsu, Ching-Yi
;
Hsieh, Ting-En
A normally-OFF GaN metal-insulator-gate high electron mobility transistors with fluorine doped gate insulator has been fabricated using standard ion implantation technique. Fluorine ions with negative charges were doped lightly into both the gate insulator and the partially recessed barrier layer, resulting in high positive threshold voltage (V-th) for the device, meanwhile preserving low ON-resistance. Compared to the fluorine-free and recess-free device, only about 16% increase of ON-resistance was observed for the F- doped devices. The fabricated F- doped device exhibits a threshold voltage of +0.68 V at I-Ds = 5 mu A/mm, a current density of 620 mA/mm, an OFF-state breakdown voltage of 800 V, and high ON/OFF current ratio of 10(10). For thermal stability consideration of fluorine dopant, the V-th-thermal stability test and positive bias temperature instability test were also discussed.
Performance Enhancement of Flip-Chip Packaged AlGaN/GaN HEMTs Using Active-Region Bumps-Induced Piezoelectric Effect
(2014-07-01)
Tsai, Szu-Ping
;
Hsu, Heng-Tung
;
Chiang, Che-Yang
;
Tu, Yung-Yi
;
Chang, Chia-Hua
We experimentally investigated the impact of different bump patterns on the output electrical characteristics of flip-chip (FC) bonded AlGaN/GaN high-electron mobility transistors in this letter. The bump patterns were designed and intended to provide different levels of tensile stress due to the mismatch in the coefficient of thermal expansion between the materials. After FC packaging, a maximum increase of 4.3% in saturation current was achieved compared with the bare die when proper arrangement of the bumps in active region was designed. In other words, a 17% improvement has been observed on the optimized bump pattern over the conventional bump pattern. To the best of our knowledge, this is the first letter that investigates the piezoelectric effect induced by FC bumps leading to the enhancement in device characteristics after packaging.
Performance Enhancement of Flip-Chip Packaged AlGaN/GaN HEMTs Using Active-Region Bumps-Induced Piezoelectric Effect
(2014-07-01)
Tsai, Szu-Ping
;
Hsu, Heng-Tung
;
Chiang, Che-Yang
;
Tu, Yung-Yi
;
Chang, Chia-Hua
We experimentally investigated the impact of different bump patterns on the output electrical characteristics of flip-chip (FC) bonded AlGaN/GaN high-electron mobility transistors in this letter. The bump patterns were designed and intended to provide different levels of tensile stress due to the mismatch in the coefficient of thermal expansion between the materials. After FC packaging, a maximum increase of 4.3% in saturation current was achieved compared with the bare die when proper arrangement of the bumps in active region was designed. In other words, a 17% improvement has been observed on the optimized bump pattern over the conventional bump pattern. To the best of our knowledge, this is the first letter that investigates the piezoelectric effect induced by FC bumps leading to the enhancement in device characteristics after packaging.
The Effect of Surface Passivation on the Electrical Performance of AlG aN/GaNHEMTs with Slant Field Plates
(2016)
Hsu, Heng-Tung
;
Lin, Yueh-Chin
;
Huang, Lu-Che
;
Chang, Chia-Hua
;
Hsieh, Ting-En