Browsing by Author "Hsieh, Tung-Ying"

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A sandwiched buffer layer enabling pulsed ultraviolet- and visible-laser annealings for direct fabricating poly-Si field-effect transistors on the polyimide
(2017-07-10)
Kao, Ming-Hsuan
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Huang, Wen-Hsien
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Shieh, Jia-Min
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Shen, Chang-Hong
;
Lee, Pei-Kang
A sandwiched buffer layer of SiO2/Al/SiO2 enables ultraviolet-laser crystallization and visible-laser activation for direct fabrication of a poly-Si flexible field-effect-transistor (fFET) on polyimides. The buffer layer can produce heat accumulation and laser reflection from the Al/SiO2 interface to facilitate grain growth and contact resistance reduction of poly-Si without damaging the polyimide substrate. The feature size of poly-Si fFET has shrunk to 400nm via laser annealing, with the on/off current-ratio exceeding 5 x 10(6) and a subthreshold swing of 190 mV/dec. Moreover, the transfer characteristics of fFET by tension stress can be maintained until the bending radius reaches over 15 mm. Published by AIP Publishing.
a-SiGeC Thin Film Photovoltaic Enabled Self-Power Monolithic 3D IC Under Indoor Illumination
(2016)
Kao, Ming-Hsuan
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Yang, Chih-Chao
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Wu, Tsung-Ta
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Hsieh, Tung-Ying
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Huang, Wen-Hsieh
Low temperature a-SiGeC thin film photovoltaic (TFPV) ambient light-energy harvesters monolithically integrated with high performance 3D sequentially stackable device were demonstrated in this article. The 3D stackable device with threshold voltage engineering and driving current boosting technologies enable excellent current controllability to achieve low I-off and high I-on operation condition for integrated circuit design. The monolithically stacking of Si thin-film energy harvester, which provide output power (21.93uW/cm(2)) under 450 lux indoor illumination, envisions self-power and low cost 3D(+)IC for internet of things.
Charge-trap non-volatile memories fabricated by laser-enabled low-thermal budget processes
(2015-11-02)
Huang, Wen-Hsien
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Shieh, Jia-Min
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Pan, Fu-Ming
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Yang, Chih-Chao
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Shen, Chang-Hong
We fabricated charge-trap non-volatile memories (NVMs) using low thermal budget processes, including laser-crystallization of poly-Si thin film, chemical vapor deposition deposition of a stacked memory layer, and far-infrared-laser dopant activation. The thin poly-Si channel has a low defect-density at the interface with the bulk, resulting in a steep subthreshold swing for the NVM transistors. The introduction of the stacked SiO2/AlOxNy tunnel layer and the SiNx charge-trap layer with a gradient bandgap leads to reliable retention and endurance at low voltage for the NVMs. The low thermal budget processes are desirable for the integration of the nano-scaled NVMs into system on panels. (C) 2015 AIP Publishing LLC.
Enabling n-type polycrystalline Ge junctionless FinFET of low thermal budget by in situ doping of channel and visible pulsed laser annealing
(2017-02)
Huang, Wen-Hsien
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Shieh, Jia-Min
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Kao, Ming-Hsuan
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Shen, Chang-Hong
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Huang, Tzu-En
A low-thermal-budget n-type polycrystalline Ge (poly-Ge) channel that was prepared by plasma in-situ-doped nanocrystalline Ge (nc-Ge) and visible pulsed laser annealing exhibits a high electrically active concentration of 2 x 10(19) cm(-3) and a narrow Raman FWHM of 3.9 cm(-1). Furthermore, the fabricated n-type poly-Ge junctionless FinFET (JL-FinFET) shows an I-on/I-off ratio of 6 x 10(4), V-th of % -0.3 V, and a subthreshold swing of 237mV/dec at V-d of 1V and DIBL of 101mV/V. The poly-Ge JL-FinFET with a high-aspect-ratio fin channel is less sensitive to V-th roll-off and subthreshold-swing degradation as the gate length is scaled down to 50 nm. This low-thermal-budget JL-FinFET can be integrated into three-dimensional sequential-layer integration and flexible electronics. (C) 2017 The Japan Society of Applied Physics
First Fully Functionalized Monolithic 3D(+) IoT Chip with 0.5 V Light-electricity Power Management, 6.8 GHz Wireless-communication VCO, and 4-layer Vertical ReRAM
(2016-01-01)
Hsueh, Fu-Kuo
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Shen, Chang-Hong
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Shieh, Jia-Min
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Li, Kai-Shin
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Chen, Hsiu-Chih
For the first time, we report low-cost heterogeneously integrated sub-40nm epi-like Si monolithic internet of thins (IoT) 3D(+)-IC with wireless communication, light-electricity power management and vertical ReRAM (VRRAM) modules. High current driving multi-channel 3D(+) UTB-MOSFETs (600 mu A/282 mu A@V-G = +/- 1V for 10-channel P/N FETs) was fabricated by low thermal budget super-CMP-planarized visible laser-crystallized epi-like Si channel and CO2 far-infrared laser annealing (CO2-FIR-LA) activation technologies that support a 6.8GHz high frequency VCO circuits, 0.5V low-voltage power management circuit and drives 20nm 4-layer VRRAM (Set/Reset <1.2V/1.8V, 3-bits/cell). This unique TSV-free monolithic 3D(+)IC process provides the superiority in 3D hetero-integration; we successfully integrate these circuits in a low cost, small footprint, fully functionalized 3D(+) IoT chip.
High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits
(2017-05-02)
Wu, Tsung-Ta
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Huang, Wen-Hsien
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Yang, Chih-Chao
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Chen, Hung-Chun
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Hsieh, Tung-Ying
Development of manufacture trend for TFTs technologies has focused on improving electrical properties of films with the cost reduction to achieve commercialization. To achieve this goal, high-performance sub-50 nm TFTs-based MOSFETs with ON-current (I-on)/subthreshold swing (S.S.) of 181 mu A/mu m/107 mV/dec and 188 mu A/mu m/98 mV/dec for NMOSFETs and PMOSFETs in a monolithic 3D circuit were demonstrated by a low power with low thermal budget process. In addition, a stackable static random access memory (SRAM) integrated with TFTs-based MOSFET with static noise margins (SNM) equals to 390 mV at V-DD = 1.0 V was demonstrated. Overall processes include a low thermal budget via ultra-flat and ultra-thin poly-Si channels by solid state laser crystallization process, chemical-mechanical polishing (CMP) planarization, plasma-enhanced atomic layer deposition (ALD) gate stacking layers and infrared laser activation with a low thermal budget. Detailed material and electrical properties were investigated. The advanced 3D architecture with closely spaced inter-layer dielectrics (ILD) enables high-performance stackable MOSFETs and SRAM for power-saving IoT/mobile products at a low cost or flexible substrate.
Junction-less poly-Ge FinFET and charge-trap NVM fabricated by laser-enabled low thermal budget processes
(2016-06-13)
Huang, Wen-Hsien
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Shieh, Jia-Min
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Shen, Chang-Hong
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Huang, Tzu-En
;
Wang, Hsing-Hsiang
A doping-free poly-Ge film as channel material was implemented by CVD-deposited nano-crystalline Ge and visible-light laser crystallization, which behaves as a p-type semiconductor, exhibiting holes concentration of 1.8 x 10(18) cm(-3) and high crystallinity (Raman FWHM similar to 4.54 cm(-1)). The fabricated junctionless 7 nm-poly-Ge FinFET performs at an I-on/I-off ratio over 10(5) and drain-induced barrier lowering of 168mV/ V. Moreover, the fast programming speed of 100 mu s-1 ms and reliable retention can be obtained from the junctionless poly-Ge nonvolatile-memory. Such junctionless poly-Ge devices with low thermal budget are compatible with the conventional CMOS technology and are favorable for 3D sequential-layer integration and flexible electronics. Published by AIP Publishing.
Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits
(2018-01-01)
Yang, Chih-Chao
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Hsieh, Tung-Ying
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Huang, Po-Tsang
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Chen, Kuan-Neng
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Wu, Wan-Chi
A location-controlled-grain technique is presented for fabricating BEOL monolithic 3D FinFET ICs over SiO2. The grain-boundary free Si FinFETs thus fabricated exhibit steep sub-threshold swing (<70mV/doc.), high driving currents (n-type: 363 mu A/mu m and p-type: 385 mu A/mu m), and high I-on/I-off(>10(6)). According to simulation, the thickness of the interlayer dielectric plays an important role and shall be thicker than 250nm so that the sequential pulse laser crystallization process does not heat the bottom devices and interconnects to more than 400 degrees C.
Logic/Memory Hybrid 3D Sequentially Integrated Circuit Using Low Thermal Budget Laser Process
(2015)
Yang, Chih-Chao
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Hsieh, Tung-Ying
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Huang, Wen-Hsien
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Wu, Tsung-Ta
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Wang, Hsing-Hsiang
High performance 3D sequentially stackable nanowire FETs and non-volatile memories (NVMs) with threshold voltage engineering and driving current boosting technologies were demonstrated by using low thermal budget nanosecond laser crystallization and laser activation technologies. The local heating laser process without damaging the underlying device/circuit realizes the across -layer and in -layer integration of high-speed 3ps logic circuits and 1-T 100ns plasma-MONOS NVMs as well as low driving-voltage 6T SRAMs with static noise margin (SNM) of 280 mV. Such logic/memory hybrid 3D sequentially integrated circuit provides power efficient computing and storage. Moreover, the monolithically stacking of Si thin-film energy harvester envisions lower power and low cost 3D(+)IC for internet of things.
Record-high 121/62 mu A/mu m on-currents 3D stacked epi-like Si FETs with and without metal back gate
(2013)
Yang, Chih-Chao
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Chen, Szu-Hung
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Shieh, Jia-Min
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Huang, Wen-Hsien
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Hsieh, Tung-Ying
A sequential layered integration technology that can fabricate 3D stackable epi-like Si FETs with and without metal back gate (MBG) under sub-400 degrees C are proposed in this article. With laser crystallized epi-like Si and CMP thinning processes for channel fabrication, 3D stackable ultra thin body (UTB) n/p-MOSFETs with low-subthreshold swings (88 and 121 mV/dec.) and high on-currents (121 and 62 liA/Iim) are demonstrated. With additional metal back gate structure, UTB devices can be desirably operated in a positive or negative threshold voltage range with gamma values of 0.51 (n-MOSFETs) and 0.56 (p-MOSFETs) for favoring its applications in 3D logic circuits. In addition, such thin and high quality channel and metal back gate scheme is not only promising for conventional p-n junction device but also junctionless (JL) scheme, which can simplify the fabrication and achieve further scaling.