Browsing by Author "Hsieh, Wen-Hung"

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A Continuous-Time Delta-Sigma Modulator Using Feedback Resistors
(2009)
Lin, Yung-Chou
;
Hsieh, Wen-Hung
;
Hung, Chung-Chih
;
電信工程研究所
;
Institute of Communications Engineering
A third-order continuous-time delta-sigma comprised of Active-RC integrator and Gm-C integrator is presented. For the consideration of power, linearity and performance, the first integrator uses active-RC OpAmp and the others use Gm-C. To reduce the clock jitter sensitivity, we choose nonreturn-to-zero (NRZ) pulse shaping as our DAC type. For the realization of NTF zero optimization, We use resistors to reduce power Consumption. The delta-sigma modulator is implemented in standard digital 0.18-mu m CMOS process which achieves a 60-dB SNDR or 10-bits ENOB over a 1-MHz signal bandwidth at an OSR of 50. The power consumption of the continuous-time delta-sigma modulator itself is 13.7 mW from the 1.8-V supply.
A Third-Order Continuous-Time Sigma-Delta Modulator for Bluetooth
(2009)
Yang, Wen-Lin
;
Hsieh, Wen-Hung
;
Hung, Chung-Chih
;
電信工程研究所
;
Institute of Communications Engineering
This paper presents the design of a third-order continuous-time (CT) single-bit active-RC sigma-delta (Sigma Delta) modulator for Bluetooth application. Through the use of the architecture, cascade of resonators with distributed feedback (CRFB), the signal bandwidth can be improved without increasing the order of the modulator. All integrators are implemented by active-RC type to have better linearity. Furthermore, in order to reduce the effect of the clock jitter, the feedback digital-to-analog converter (DAC) shape is realized by non-return-to-zero (NRZ). The modulator is designed in a standard digital 0.18 mu m CMOS process with a chip area of 1.32x1.23 mm(2). The measurement results show that the modulator achieves 56.8dB SNDR and 60dB dynamic range over 1MHz signal bandwidth, consuming 22.2mW at 1.8V supply.