Browsing by Author "Hsieh, YT"

Now showing 1 - 7 of 7

A 125MHz 8b digital-to-phase converter
(2003)
Chou, JM
;
Hsieh, YT
;
Wu, JT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A two-stage MMSE partial PIC receiver for multiuser detection
(2001)
Wu, WR
;
Su, WS
;
Hsieh, YT
;
電信工程研究所
;
Institute of Communications Engineering
The partial parallel inteference cancellation (PIC) detector is considered as an effective yet simple receiver for multiuser detection in code-division multiple access (CDMA) systems. It cancels the multiple access interference (MAI) of the received signal partially resulted from other users. However, the optimal cancellation level which is controlled by a partial cancellation factor (PCF) is usually determined by trial and error, since no theoretical values were reported. In this paper we introduce a MMSE criterion for the two-stage partial PIC receiver to derive the optimal PCF. Simulations show that the performance of proposed methods is very close to that of empirically chosen PCF. We also demonstrate that the derived PCF is insensitive to the estimate bias of noise level and the interfering signal power.
An optimum two-stage partial parallel interference canceller for CDMA systems
(2002)
Hsieh, YT
;
Wu, WR
;
電信工程研究所
;
Institute of Communications Engineering
The parallel interference cancellation (PIC) is considered as an effective yet simple detector for multiuser communications in direct-sequence code division multiple access (DS-CDMA) systems. However, the system performance may be deteriorated due to unreliable interference estimate in early canceling stages. Thus the partial cancellation factor (PCF) is introduced to control the interference canceling level resulting in the partial PIC approach. While the PCF is critical, the existing methods for determining optimum PCF is either not general or not accurate. In this paper, we propose a method deriving a close-form solution for the optimum PCF in a two-stake partial PIC receiver. Our results apply to either power balanced or unbalanced, synchronous or asynchronous systems. Simulation results show that our theoretical optimal PCF values are closed to the empirical ones. Also, the optimal two-stage partial PIC even outperforms three-stage full PIC.
Chemical-mechanical polishing and material characteristics of plasma-enhanced chemically vapor deposited fluorinated oxide thin films
(1997-03-01)
Tseng, WT
;
Hsieh, YT
;
Lin, CF
;
Tsai, MS
;
Feng, MS
The chemical-mechanical polishing (CMP) process has been proven to be the most promising method for accomplishing global planarization. In this paper, results of chemical-mechanical polishing of fluorinated silicon dioxide (SiOF) thin films are presented. Nanohardness, elastic modulus, and bonding structure of fluorinated silicon dioxides are characterized in order to evaluate their correlations with CMP performance. The results show that under fixed chemistry and mechanical parameters, the CMP removal rate increases significantly with increasing fluorine content in the oxides due to the lower hardness and elastic modulus in the films. Higher CMP removal rate is observed for fluorinated oxides polished with slurry of pH 10 relative to pH 9. Compared with undoped oxides, SiOF films are more sentisitive to chemical and moisture attacks as reflected by the post-CMP increase in refractive index.
CMP of fluorinated silicon dioxide: Is it necessary and feasible?
(1997-02-01)
Tseng, WT
;
Hsieh, YT
;
Lin, CF
;
交大名義發表
;
National Chiao Tung University
Use of low-permittivity (low-k) fluorinated silicon dioxides (F-SiO2) for inter-metal dielectric (IMD) applications makes it necessary to evaluate the compatibility of chemical-mechanical polishing (CMP) in device fabrication. Basic material characteristics (such as adhesion, gap fill, step coverage, stress, hardness, chemical stability, moisture permeation, and wet etching rate) should be investigated thoroughly to assess CMP performance. With increasing fluorine content in the oxides, the low-k dielectric exhibits increased chemical reactivity and water absorption. These properties enhance the CMP removal rate, but degrade post-CMP material reliability and electrical performance. This article examines the CMP performance of F-SiO2 used to provide a low dielectric constant in IMD applications.
Optimal two-stage decoupled partial PIC receivers for multiuser detection
(2005-01-01)
Hsieh, YT
;
Wu, WR
;
電信工程研究所
;
Institute of Communications Engineering
Parallel interference cancellation (PIC) is considered a simple yet effective multiuser detector for direct-sequence code-division multiple-access (DS-CDMA) systems. However, system performance may deteriorate due to unreliable interference cancellation in the early stages. Thus, a partial PIC detector in which partial cancellation factors (PCFs) are introduced to control the interference cancellation level has been developed as a remedy. Although PCFs are crucial, complete solutions for their optimal values are not available. In this paper, we consider a two-stage decoupled partial PIC receiver. Using the minimum bit error rate (BER) criterion, we derive a complete set of optimal PCFs. This includes optimal PCFs for periodic and aperiodic spreading codes in additive white Gaussian channels and multipath channels. Simulation results show that our theoretical optimal PCFs agree closely with empirical ones. Our two-stage partial PIC using derived optimal PCFs outperforms not only a two-stage, but also a three-stage full PIC.
Phase averaging and interpolation using resistor strings or resistor rings for multi-phase clock generation
(2006-05-01)
Chou, JM
;
Hsieh, YT
;
Wu, JT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Circuit techniques using resistor strings (R-strings) and resistor rings (R-rings) for phase averaging and interpolation are described. Phase averaging can reduce phase errors, and phase interpolation can increase the number of available phases. In addition to the waveform shape, the averaging and the interpolation performances of the R-strings and R-rings are determined by the clock frequency normalized by a RC time constant of the circuits. To attain better phase accuracy, a smaller RC time constant is required, but at the expense of larger power dissipation. To demonstrate the resistor ring's capability of phase averaging and interpolation, a 125-MHz 8-bit digital-to-phase converter (DPC) was designed and fabricated using a standard 0.35-mu m SPQM CMOS technology. Measurement results show that the DPC attains 8-bit resolution using the proposed phase averaging and interpolation technique.