Browsing by Author "Hsieh, Yi-Bin"

Now showing 1 - 7 of 7

A fully integrated spread spectrum clock generator using a dual-path loop filter
(2006)
Kao, Yao-Huang
;
Hsieh, Yi-Bin
;
傳播研究所
;
Institute of Communication Studies
A fully integrated spread spectrum clock generator (SSCG) using the VCO direct modulation was presented. The dual-path loop filter in the phased locked loop was employed to reduce the required area of capacitance in the filter by using another charge pump circuit. In the meantime, the third charge pump was used to achieve the triangle modulation. The proposed circuit had been fabricated by TSMC 0.35um CMOS single-poly quadruple-metal process. The clock rate from 50MHz to 480MHz with center spread spectrum ratios with 0.5%-2% was verified. The size of chip area was 0.82xO.8mm(2) including the loop filter and the power consumption was 27.5mW at 400MHz.
A fully integrated spread spectrum clock generator using two-point delta-sigma modulation
(2007)
Hsieh, Yi-Bin
;
Kao, Yao-Huang
;
傳播研究所
;
Institute of Communication Studies
A new spread spectrum clock generator (SSCG) using two-point delta-sigma modulation is presented in this paper. Not only the divider is varied, but also the voltage controlled oscillator is modulated. This technique can enhance the modulation bandwidth so that the effect of EMI suppression is improved. In addition, the method of two-path is applied to the loop filter to reduce the capacitance value such that the total integration can be achieved. The proposed SSG has been fabricated in a 0.35um CMOS process. The clock of 400MHz with center spread ratios of 1.25% and 2.5% are verified. The size of chip area is 0.90x0.89 mm(2).
A fully integrated spread-spectrum clock generator by using direct VCO modulation
(2008-08-01)
Hsieh, Yi-Bin
;
Kao, Yao-Huang
;
傳播研究所
;
Institute of Communication Studies
A compact architecture for a fully-integrated spread-spectrum clock generator (SSCG) using voltage-controlled oscillator direct modulation is presented in this paper. A dual-path loop filter in the phase-locked loop is employed to reduce the size of the capacitance in the filter with the aid of an extra charge pump and a unity gain amplifier. At the same time, a third-charge pump which generates triangular waves is used to perform the function of a spread-spectrum. The proposed circuit has been fabricated using a 0.35-mu m CMOS single-poly quadruple-metal process. The clock rate from 50 to 480 MHz with a center spread range of between 0.5 % and 2 % are verified and are close to the theoretical analyses. The size of the chip area is 0.82 x 0.8 mm(2) (including the loop filter) and the power consumption was 27.5 mW at 400 MHz. Index Terms-Phase-locked loop (PLL), spread-spectrum clock generator (SSCG).
A high performance spread spectrum clock generator using two-point modulation scheme
(2008-06-01)
Kao, Yao-Huang
;
Hsieh, Yi-Bin
;
傳播研究所
;
Institute of Communication Studies
A new spread spectrum clock generator (SSCG) using two-point delta-sigma modulation is presented in this paper. Not only the divider is varied, but also the voltage controlled oscillator is modulated. This technique can enhance the modulation bandwidth so that the effect of EMI suppression is improved with lower order Sigma Delta modulator and can simultaneously optimize the jitter and the modulation profile. In addition, the method of two-path is applied to the loop filter to reduce the capacitance value such that the total integration can be achieved. The proposed SSCG has been fabricated in a 0.35 mu m CMOS process. The clock of 400 MHz with center spread ratios of 1.25% and 2.5% are verified. The peak EMI reduction is 19.73 dB for the case of 2.5%. The size of chip area is 0.90 X 0.89 mm(2).
A Low-Power and High-Precision Spread Spectrum Clock Generator for Serial Advanced Technology Attachment Applications Using Two-Point Modulation
(2009-05-01)
Kao, Yao-Huang
;
Hsieh, Yi-Bin
;
傳播研究所
;
Institute of Communication Studies
A new technique utilizing two-point (TP) modulation for a spread spectrum clock generator (SSCG) for serial advanced technology attachment is presented in which the divider ratio is varied by a digital Sigma Delta modulator, and the voltage-controlled oscillator is modulated analogically. With this technique, the modulation bandwidth is enhanced in order that the modulation profile accuracy and jitter performance caused by the Sigma Delta modulator can be improved at the same time. The order of the Sigma Delta modulator and the loop filter can be reduced to save power and area, while the electromagnetic interference (EMI) suppression still satisfies specifications. The dual-path loop filter (DL) reduces the size of the loop capacitor and enables full integration. The proposed TPDL-SSCG has been fabricated in a 0.18-mu m CMOS process. The size of the chip area is 0.44 x 0.48 mm(2). The circuit produces a clock of 1.5 GHz with a down-modulation ratio of 0.5%, 10.14 dB EMI of reduction, 5.485 ps rms jitter, and 35 ps peak-to-peak jitter. The power consumption, excluding an output buffer, is only 15.3 mW.
A new spread spectrum clock generator for SATA using double modulation schemes
(2007)
Hsieh, Yi-Bin
;
Kao, Yao-Huang
;
傳播研究所
;
Institute of Communication Studies
A new spread spectrum clock generator (SSCG) using double modulation is presented in this paper. Not only the divider is varied, but also the voltage controlled oscillator is modulated. This technique can enhance the modulation bandwidth so that the effect of EMI suppression is improved and can optimize the jitter caused by the Sigma Delta modulator. In addition, the method of two-path is applied to reduce the capacitance value such that the total integration can be achieved. The proposed SSCG has been fabricated in a 0.18um CMOS process. The clock of 1.5GHz with down spread ratio of 0.5% is realized for applications to serial ATA. The 19.63dB EMI reduction (RBW=10KHz) and 35ps-pp period jitter are achieved in this study. The size of chip area is 0.44x0.48mm(2). The power consumption is 27mW.
A wide input-range Sigma Delta modulator for applications to spread-spectrum clock generator
(2006)
Kao, Yao-Huang
;
Hsieh, Yi-Bin
;
傳播研究所
;
Institute of Communication Studies
A spread-spectrum clock generator (SSCG) using fractional-N phase-locked loop (PLL) with an extended range sigma-delta (EA) modulator is presented in this paper. The proposed EA modulator simply adds an extra output bit in the first stage modulator. It can enlarge the input range about three times as compared to the conventional modulator and solve the saturation problem when the input exceeds the boundary of the conventional modulator. The proposed SSCG has been fabricated in TSMC 0.35-um double-poly quadruple-metal CMOS process with output frequency of 300MHz. The active area is 0.63x4.62 mm(2) and the power consumption is 17.5mW.