Browsing by Author "Hsieh, Zong-Han"

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A Brain-Computer Interface with Real-Time Independent Component Analysis for Biomedical Applications
(2012)
Hsieh, Zong-Han
;
Fang, Wai-Chi
;
Jung, Tzyy-Ping
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a brain-computer interface with real-time independent component analysis for biomedical applications. EEG-based BCI technology using cell-phone and Bluetooth transmission of bio-signals has been established in previous studies, and experimental results show that subjects should avoid eye blink who are under test to increase the accuracy. In order to enhance the dialing system, the authors integrate a real-time ICA chip to artifacts arising from eye blinking. The designed system enables the acquisition and subsequent ICA elaboration signals in real-time, the result shows suitable for BCI applications. The efficiency of the implemented technique has been experimentally demonstrated.
A Highly-Integrated Biomedical Multiprocessor System for Portable Brain-Heart Monitoring
(2011)
Chua, Ericson
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Fang, Wai-Chi
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Chen, Chiu-Kuo
;
Fu, Chih Chung
;
Tseng, Shao-Yen
In this paper, a highly-integrated multiprocessor chip design enabling the real-time processing of biomedical signals in portable brain-heart monitoring systems is presented. The architecture comprises a novel diffuse optical tomography (DOT) processor for taking brain imaging, an independent component analysis (ICA) processor for removing artifacts of brain electroencephalogram (EEG) signals, and a heart rate variability (HRV) analysis processor for monitoring heart electrocardiogram (ECG) signals. The multiprocessor chip implemented in 65nm CMOS technology comprises 368k gates and occupies a core area of 462k mu m(2). Simulated power consumption using a full operation test case reports 3.6mW under the condition of 1.0V core supply voltage and 24MHz clock operating frequency.
A Low Power Independent Component Analysis Processor in 90nm CMOS Technology for EEG Signal Processing Systems
(2011)
Chen, Chiu-Kuo
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Wang, Yi-Yuan
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Hsieh, Zong-Han
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Chua, Ericson
;
Fang, Wai-Chi
This paper presents a low-power VLSI implementation of a 4-channel independent component analysis (ICA) processor for portable EEG signal processing applications. The low-power scheme employed for this ICA chip is based on power gating and clock gating by utilizing Cadence common power flow (CPF) low-power methodology and also according to the characteristics of ICA training behavior using different training window sizes. The proposed low power ICA processor can separate EEG and mixed EEG-like super-Gaussian signals in real time. The chip can be operated at up to 60MHz working frequency and a maximum sampling rate of 9.394 KHz for EEG signals. The power consumption of this chip is 0.690 mW during training under the condition of 0.9V supply voltage and 10 MHz operating frequency using UMC 90nm High-Vt CMOS technology. The total chip area is 1230 x 1230 mu m(2).
A Novel Readout Chip with Extendability for Multi-Channel EEG Measurement
(2013-01-01)
Chen, Yi-Chung
;
Tsai, Chung-Han
;
Hsieh, Zong-Han
;
Fang, Wai-Chi
;
電子工程學系及電子研究所
This paper proposes an extendable front-end readout chip (EFRC) for electroencephalography (EEG) measurements. An EFRC is developed for EEG measurement with features including low power consumption, a high signal-to-noise ratio, and highly efficient chip area usage. A chopper-stabilized differential difference amplifier (CHDDA) is used in the first stage to amplify signals and then during another adjustable amplification stage and filter are used to process biomedical signals. A 10-bit successive approximation register analog-to-digital converter (SAR-ADC) then links to the back-end for digital signal processing. In the last stage, shift-register pairs are used to transmit data to the next chip and receive data from the previous chip. The shift register design allows the number of channels to be extended. A TSMC 0.18 um CMOS process is used to design the EFRC and it operates with a 1.8 V supply voltage. The results shows that the total power consumption for the EFRC chip is approximately 80.268 uW and the chip area is approximately 944 x 863 um(2).
A Wireless Readout Front-End Device for Portable EEG Acquisition System
(2013)
Chen, Yi-Chung
;
Hsieh, Zong-Han
;
Fang, Wai-Chi
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, the 32-channel readout front-end device with a Bluetooth 2.0 module and a MSP430 ultra-low power microcontroller for portable Electroencephalograph (EEG) acquisition is presented. In addition to the consideration of low power, low noise, and high efficient chip area usage, the extendable readout front-end chip is presented with a design of chopper-stabilized differential difference amplifier (CHDDA) for high common mode rejection ratio (CMRR) and the 10-bit successive approximation register analog-to-digital converter (SAR-ADC) for high Signal-to-Noise Ratio (SNR). The power consumption of each readout chip is about 80.268 mu W, and the total system is about 134.6 mW under the power supply of +/- 1.8 V.