Browsing by Author "Hsien, SK"

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Improved immunity to plasma damage in ultrathin nitrided oxides
(2000-01-01)
Chen, CC
;
Lin, HC
;
Chang, CY
;
Liang, MS
;
Chien, CH
Plasma-induced damage in various 3-nm thick gate oxides (i.e., pure O-2 and N2O-nitrided oxides) was investigated by subjecting both nMOS and pMOS antenna devices to a photoresist ashing step after metal pad definition, Gate leakage current measurements indicated that large leakage current occurs at the wafer center as well as at the wafer edge for pMOS devices, while it occurs only at the wafer center for nMOS devices, These interesting observations could be explained by the polarity dependence of ultrathin oxides in charge-to-breakdown measurements. Additionally, ultrathin N2O-nitrided oxides show superior immunity to charging damage, especially for pMOS devices.
Oxide thickness dependence of plasma charging damage
(1999-03-01)
Lin, HC
;
Chen, CC
;
Wang, MF
;
Hsien, SK
;
Chien, CH
Charging damage induced in oxides with thickness ranging from 8.7 to 2.5 nm is investigated. Results of charge-to-breakdown (Q(bd)) measurements performed on control devices indicate that the polarity dependence increases with decreasing oxide thickness at both room and elevated temperature (180 degrees C) conditions. As the oxide thickness is thinned down below 3nm, the Q(bd) becomes very sensitive to the stressing current density and temperature. Experimental results show that severe antenna effect would occur during plasma ashing treatment in devices with gate oxides as thin as 2.6 nm. It is concluded that high stressing current level, negative plasma charging, and high process temperature are key factors responsible for the damage. (C) 1999 Elsevier Science Ltd. All rights reserved.
Plasma-induced charging damage in ultrathin (3-nm) gate oxides
(2000-07-01)
Chen, CC
;
Lin, HC
;
Chang, CY
;
Liang, MS
;
Chien, CH
Plasma-induced damage in various 3-nm-thick gate oxides (i.e., pure oxides and N2O-nitrided oxides) was investigated by subjecting both nMOS and pMOS antenna devices to a photoresist ashing step after metal pad definition. Both charge-to-break-down and gate leakage current measurements indicated that large leakage current occurs at the wafer center as well as the wafer edge for pMOS devices, while only at the wafer center for nMOS devices. These interesting observations could be explained by the strong polarity dependence of ultra-thin oxides in charge-to breakdown measurements of nMOS devices. In addition, pMOS devices were found to be more susceptible to charging damage, which can be attributed to the intrinsic polarity dependence in tunneling current between n- and p-MOSFET,s. More importantly, our experimental results demonstrated that stress-induced leakage current (SILC) caused by plasma damage can be significantly suppressed in N2O-nitrided oxides, compared to pure oxides, especially for pMOS devices. Finally, nitrided oxides were also found to be more robust when subjected to high temperature stressing. Therefore, nitrided oxides appear to be very promising for reducing plasma charging damage in future ULSI technologies employing ultrathin gate oxides.
The role of a resist during O-2 plasma ashing and its impact on the reliability evaluation of ultrathin gate oxides
(1997-07-01)
Chien, CH
;
Chang, CY
;
Lin, HC
;
Chang, TF
;
Hsien, SK
Resists are regarded as protective layers for underlying devices during plasma ashing. In previous studies, resists were deliberately removed by a wet etching process prior to plasma exposure in an effort to achieve significant device degradation. In this paper we report that, contrary to conventional belief, devices with a resist overlayer actually suffer from more severe degradation than those without a resist covering. This resist-enhanced degradation effect, although not observed for devices with a thick gate oxide of 8 nm, becomes significant as the oxide thickness is scaled down below 6 nm. The most severe device degradation is found to be located at the center of the wafer and is found to increase with increasing antenna area ratio. Damage is also found to occur not during the overashing period, but primarily during the initial ashing stage when the resist is still on the electrodes. Using a combination of a simple equivalent capacitor circuit model and the self-adjustment behavior of potential between the wafer surface and substrate, good correlation with the experimental results is obtained.
The role of resist for ultrathin gate oxide degradation during O-2 plasma ashing
(1997-05-01)
Chien, CH
;
Chang, CY
;
Lin, HC
;
Chiou, SG
;
Huang, TY
During ashing process, resist has been intuitively regarded as a protection layer and deliberately removed in previous studies by wet process prior to plasma exposure in an effort to amplify the damage effect, Recently, we found instead that resist does not simply act as a protection layer, This newly observed phenomenon cannot be explained by the well-known electron shading effect which should not affect the area-intensive antenna structure used in our study, In this letter, we hypothesize that this resist-related charging damage is determined by the plasma potential adjustment difference between those devices with and without resist overlayer, The experimental results show a good correlation with our explanation, To be specific, severe antenna area ratio (ARR) dependent degradation of thin gate oxide is induced during the initial ashing stage while the resist is still on the electrodes, not during the overashing period.
The role of resist for ultrathin gate oxide degradation during O-2 plasma ashing
(1997-05-01)
Chien, CH
;
Chang, CY
;
Lin, HC
;
Chiou, SG
;
Huang, TY
During ashing process, resist has been intuitively regarded as a protection layer and deliberately removed in previous studies by wet process prior to plasma exposure in an effort to amplify the damage effect, Recently, we found instead that resist does not simply act as a protection layer, This newly observed phenomenon cannot be explained by the well-known electron shading effect which should not affect the area-intensive antenna structure used in our study, In this letter, we hypothesize that this resist-related charging damage is determined by the plasma potential adjustment difference between those devices with and without resist overlayer, The experimental results show a good correlation with our explanation, To be specific, severe antenna area ratio (ARR) dependent degradation of thin gate oxide is induced during the initial ashing stage while the resist is still on the electrodes, not during the overashing period.