Browsing by Author "Hsu, CCH"

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A novel leakage current separation technique in a direct Tunneling regime gate oxide SONOS memory cell
(2003)
Chung, SS
;
Chiang, PY
;
Chou, G
;
Huang, CT
;
Chen, P
In this paper, data retention for various top and bottom oxide (tunnel oxide) SONOS cells has been extensively investigated. For the first time, a leakage current separation technique has been developed to distinguish the two leakage current components via thermionic and direct tunneling (DT) in the ONO layer. Results show that the short-term leakage is dominated by the direct tunneling, while the long-term leakage is dominated by the thermionic emission. The direct tunneling through either tunnel or blocking oxide can also be identified experimentally. These results are useful toward an understanding of the scaling of SONOS cell with focus on its reliabilities.
A numerical model for simulating MOSFET gate current degradation by considering the interface state generation
(1996)
Yih, CM
;
Chung, SS
;
Hsu, CCH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Investigation of the gate dielectric oxidation treatment in trench gate power devices
(2001)
Lin, MJ
;
Liaw, CE
;
Chang, JJ
;
Chang, FL
;
Hsu, CCH
In respect of trench gate power devices, it is difficult to achieve satisfactory gate oxide leakage current, breakdown voltage and reliability characteristics. Trench etching process induced silicon surface damage, convex corner and contamination, which will degrade the silicon dioxide quality. It is convinced that post etching treatment including sacrificial oxidation and chemical dry ashing can improve the gate oxide quality significantly. In this article, we study the treatment of a trench capacitor with sacrificial oxidation and classify the effect of each parameter in the oxidation process. The benefit of N2O annealing after gate oxidation will also be discussed. The evaluations of I-V and CV characteristics are the main considerations of the gate oxide quality in this research.