Browsing by Author "Hsu, Chih-Hsiang"

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A 2.56 Gb/s Soft RS (255,239) Decoder Chip for Optical Communication Systems
(2014-07-01)
Lin, Yi-Min
;
Hsu, Chih-Hsiang
;
Chang, Hsie-Chia
;
Lee, Chen-Yi
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電子工程學系及電子研究所
Due to high transmission rate requirement for optical communication systems, the growing uncertainty of received signals results in the limited transmission distance. In this paper, a decision-confined soft RS decoder chip is proposed to enhance the error correcting performance with area-efficient architectures. Instead of generating numerous possible candidate codewords and determining the most likely one as output codeword, our approach produces only one codeword by confining the degree of error location polynomial. Therefore, hardware complexity is significantly reduced by eliminating decision making unit. Moreover, an iteration-reduced RiBM algorithm is provided to enlarge the coding gain by using more least reliable positions (LRPs) in the limited operation latency. According to simulation results, our proposed soft RS (255, 239; 8) decoder with 5 LRPs outperforms 0.4 dB at 10(-4) codeword error rate (CER) as compared to hard RS decoders. Implemented in standard CMOS 90 nm technology, the soft decoder chip can achieve 2.56 Gb/s throughput with similar complexity as a hard decoder. It can fit well for 10-40 Gb/s with 16 RS decoders in optical fiber systems and 2.5 Gb/s GPON applications.
A MPCN-Based Parallel Architecture in BCH Decoders for NAND Flash Memory Devices
(2011-10-01)
Lin, Yi-Min
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Yang, Chi-Heng
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Hsu, Chih-Hsiang
;
Chang, Hsie-Chia
;
Lee, Chen-Yi
According to large-page-size and random-bit-error characteristics, long-block-length Bose-Chaudhuri-Hochquenghem (BCH) decoders are applied to realize error correction in NAND Flash memory devices. To accelerate the decoding process in an area-efficient architecture, a parallel architecture with minimal polynomial combinational network (MPCN) for long BCH decoders is presented in this brief. The proposed design utilizes MPCNs to replace constant finite-field multipliers, which dominate the hardware complexity of the high-parallel Chien search architecture. Furthermore, both the syndrome calculator and the Chien search can be merged by exploiting our MPCN-based architecture, leading to significant hardware complexity reduction. From the synthesis results in the 90-nm CMOS technology, the MPCN-based joint syndrome calculation and Chien search has 46.7% gate count saving for parallel-32 BCH (4603, 4096; 39) decoder in contrast with the straightforward design.
Characterization of Silicon Photonics Modulator Integration and High Efficiency Testing Platform
(2019-01-01)
Chen, Shang-Chun
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Wun, Sin-Jhu
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Hsu, Chih-Hsiang
;
Lin, Chen-Yu
;
Zhang, Jie
We successfully establish a silicon photonics device manufacturing and testing platform in 200mm SOI wafer. We integrate modulator and driver chip to show 30Gbis PAM4 capability. A fully-automatic wafer level characterization process is built up for all optical devices in surface coupling method.