Browsing by Author "Hsu, Chung-Wei"

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3D resistive RAM cell design for high-density storage class memory-a review
(2016-06)
Hudec, Boris
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Hsu, Chung-Wei
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Wang, I-Ting
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Lai, Wei-Li
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Chang, Che-Chia
In this article, we comprehensively review recent progress in the ReRAM cell technology for 3D integration focusing on a material/device level. First we briefly mention pioneering work on high-density crossbar ReRAM arrays which paved the way to 3D integration. We discuss the two main proposed 3D integration schemes-3D horizontally stacked ReRAM vs 3D Vertical ReRAM and their respective advantages and disadvantages. We follow with the detailed memory cell design on important work in both areas, utilizing either filamentary or interface-limited switching mechanisms. We also discuss our own contributions on HfO2-based filamentary 3D Vertical ReRAM as well as TaOx/TiO2 bilayer-based self-rectifying 3D Vertical ReRAM. Finally, we summarize the present status and provide an outlook for the nearterm future.
3D Synaptic Architecture with Ultralow sub-10 fJ Energy per Spike for Neuromorphic Computation
(2014)
Wang, I-Ting
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Lin, Yen-Chuan
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Wang, Yu -Fen
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Hsu, Chung-Wei
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Hou, Tuo-Hung
A high-density 3D synaptic architecture based on self-rectifying Ta/TaOx/TiO2/Ti RRAM is proposed as an energy- and cost-efficient neuromorphic computation hardware. The device shows excellent analog synaptic features that can be accurately described by the physical and compact models. Ultra-low energy consumption comparable to that of a biological synapse (<10 fJ/spike) has been demonstrated for the first time.
3D Vertical TaOx/TiO2 RRAM with over 10(3) Self-Rectifying Ratio and Sub-mu A Operating Current
(2013-01-01)
Hsu, Chung-Wei
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Wan, Chia-Chen
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Wang, I-Ting
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Chen, Mei-Chin
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Lo, Chun-Li
The 3D double-layer vertical RRAM with ultralow sub-mu A operating current and high self-rectifying ratio over 10(3) has been demonstrated for the first time. This Ta/TaOx/TiO2/Ti interfacial switching device overcomes the intrinsic trade-off between operating current and variability in filamentary RRAMs and shows promising potential for high-density data storage.
Bipolar Ni/TiO2/HfO2/Ni RRAM With Multilevel States and Self-Rectifying Characteristics
(2013-07-01)
Hsu, Chung-Wei
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Hou, Tuo-Hung
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Chen, Mei-Chin
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Wang, I-Ting
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Lo, Chun-Li
To be compatible with 3-D vertical crossbar arrays, a TiO2/HfO2 bilayer resistive-switching memory (RRAM) cell sandwiched between Ni electrodes is developed. The proposed device has numerous highly desired features for the implementation of 3-D vertical RRAM, including: 1) stable bipolar resistive switching; 2) forming free; 3) self-compliance; 4) self-rectification; 5) multiple resistance states; and 6) room-temperature process. The resistive switching and current rectification are attributed to oxygen vacancy migration in HfO2 and potential barrier modulation of the asymmetric TiO2/HfO2 tunnel barrier. The rectification ratio up to 10(3) is capable of realizing a single-crossbar array up to 16 Mb for future high-density storage class memory applications.
Bipolar Nonlinear Ni/TiO(2)/Ni Selector for 1S1R Crossbar Array Applications
(2011-10-01)
Huang, Jiun-Jia
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Tseng, Yi-Ming
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Hsu, Chung-Wei
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Hou, Tuo-Hung
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電子工程學系及電子研究所
A bipolar nonlinear selector to suppress the sneak current in the crossbar array has been fabricated using a simple Ni/TiO(2)/Ni metal-insulator-metal structure. The highly nonlinear current-voltage characteristics are realized by the Schottky emission over the Ni/TiO(2) barriers. The series connection with an HfO(2)-resistive memory device shows reproducible bipolar resistive switching. The maximum array size with at least 10% read margin is projected to exceed megabits. This letter demonstrates the promise of the compact one selector-one resistor (1S1R) cell structure for high-density crossbar array applications.
Bipolar Nonlinear Ni/TiO2/Ni Selector for 1S1R Crossbar Array Applications
(2011-10-01)
Huang, Jiun-Jia
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Tseng, Yi-Ming
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Hsu, Chung-Wei
;
Hou, Tuo-Hung
;
電子工程學系及電子研究所
A bipolar nonlinear selector to suppress the sneak current in the crossbar array has been fabricated using a simple Ni/TiO2/Ni metal-insulator-metal structure. The highly nonlinear current-voltage characteristics are realized by the Schottky emission over the Ni/TiO2 barriers. The series connection with an HfO2-resistive memory device shows reproducible bipolar resistive switching. The maximum array size with at least 10% read margin is projected to exceed megabits. This letter demonstrates the promise of the compact one selector-one resistor (1S1R) cell structure for high-density crossbar array applications.
Categorization of Multilevel-Cell Storage-Class Memory: An RRAM Example
(2015-08-01)
Liu, Jen-Chieh
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Hsu, Chung-Wei
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Wang, I-Ting
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Hou, Tuo-Hung
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電子工程學系及電子研究所
This paper provides new insights into the effect of device characteristics on multilevel-cell (MLC) operation, aiming at potential benefits, such as the reduction of write latency and peripheral circuit design overhead. A general categorization of the MLC-operating schemes in storage-class memory (SCM) is proposed to connect the total number of write inputs with fundamental device properties. The categorization method is validated using two resistive random access memory devices based on different switching mechanisms. Favorable device characteristics and the corresponding simplified MLC operating schemes are addressed to facilitate future development of MLC SCM.
Crossbar array of selector-less TaOx/TiO2 bilayer RRAM
(2015-11-01)
Chou, Chun-Tse
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Hudec, Boris
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Hsu, Chung-Wei
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Lai, Wei-Li
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Chang, Chih-Cheng
In this work, we have implemented self-rectifying TaOx/TiO2 REAM in a selector-less 6 x 6 crossbar array with various desiring features, including: (1) simple fabrication using only three masks, (2) high self-rectifying ratio up to 10(3) for sneak current suppression, (3) stable bipolar resistive-switching characteristics without the need for electro-forming and current compliance, (4) data retention time over 10(4) s, and (5) robust READ and WRITE disturb immunity. Finally, an achievable array size of 1 Mb was simulated using an All-LPU read scheme and a V/3 write scheme. (C) 2015 Elsevier Ltd. All rights reserved.
Flexible One Diode-One Resistor Crossbar Resistive-Switching Memory
(2012-04-01)
Huang, Jiun-Jia
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Hou, Tuo-Hung
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Hsu, Chung-Wei
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Tseng, Yi-Ming
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Chang, Wen-Hsiung
We report the first demonstration of a flexible one diode-one resistor (1D1R) resistive-switching (RS) memory cell capable of high-density crossbar array implementation at an extremely low cost. A Ti/TiO2/Pt diode with a large rectifying ratio and a stable Ni/HfO2/Pt unipolar RS memory element have been fabricated on a polyimide substrate using only room-temperature processes. No significant degradation of the rectifying ratio of the TiO2 diode and the cycling variations, retention, and read disturb immunity of the HfO2 memory was observed in the bending state. The series 1D1R cell shows highly reproducible unipolar RS because of the low reset current of the HfO2 memory, which greatly mitigates the adverse effect of diode series resistance. Furthermore, the 1D1R cell can effectively suppress read interference and realize a crossbar array as large as 512 kbit. (C) 2012 The Japan Society of Applied Physics
Homogeneous barrier modulation of TaOx/TiO2 bilayers for ultra-high endurance three-dimensional storage-class memory
(2014-04-25)
Hsu, Chung-Wei
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Wang, Yu-Fen
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Wan, Chia-Chen
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Wang, I-Ting
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Chou, Chun-Tse
Three-dimensional vertical resistive-switching random access memory (V-RRAM) is the most anticipated candidate for fulfilling the strict requirements of the disruptive storage-class memory technology, including low bit cost, fast access time, low-power nonvolatile storage, and excellent endurance. However, an essential self-selecting resistive-switching cell that satisfies these requirements has yet to be developed. In this study, we developed a TaOx/TiO2 double-layer V-RRAM containing numerous highly desired features, including: (1) a self-rectifying ratio of up to 10(3) with a sub-mu A operating current, (2) little cycle-to-cycle and layer-to-layer variation, (3) a steep vertical sidewall profile for high-density integration, (4) forming-free and self-compliance characteristics for a simple peripheral circuit design, and (5) an extrapolated endurance of over 10(15) cycles at 100 degrees C. Furthermore, the switching and self-rectifying mechanisms were successfully modeled using oxygen ion migration and homogeneous barrier modulation. We also suggest the new possibility of monolithically integrating working and storage memory by exploiting a unique tradeoff between retention time and endurance.
Investigating MLC Variation of Filamentary and Non-filamentary RRAM
(2014-01-01)
Liu, Jen-Chieh
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Wang, I-Ting
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Hsu, Chung-Wei
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Luo, Wun-Cheng
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Hou, Tuo-Hung
n One Selector-One Resistor (1S1R) Crossbar Array for High-density Flexible Memory Applications
(2011)
Huang, Jiun-Jia
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Tseng, Yi-Ming
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Luo, Wun-Cheng
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Hsu, Chung-Wei
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Hou, Tuo-Hung
Lack of a suitable selection device to suppress sneak current has impeded the development of 4F(2) crossbar memory array utilizing stable and scalable bipolar resistive-switching. We report a high-performance nonlinear bipolar selector realized by a simple Ni/TiO2/Ni MIM structure with a high current density of 10(5) A/cm(2), and a Ni/TiO2/Ni/HfO2/Pt vertically stacked 1S1R cell capable of gigabit memory implementation. Furthermore, the demonstration of 1S1R array fabricated completely at room temperature on a plastic substrate highlights the promise of future extremely low-cost flexible nonvolatile memory.
One Selector-One Resistor (1S1R) Crossbar Array for High-density Flexible Memory Applications
(2011)
Huang, Jiun-Jia
;
Tseng, Yi-Ming
;
Luo, Wun-Cheng
;
Hsu, Chung-Wei
;
Hou, Tuo-Hung
Lack of a suitable selection device to suppress sneak current has impeded the development of 4F(2) crossbar memory array utilizing stable and scalable bipolar resistive-switching. We report a high-performance nonlinear bipolar selector realized by a simple Ni/TiO2/Ni MIM structure with a high current density of 10(5) A/cm(2), and a Ni/TiO2/Ni/HfO2/Pt vertically stacked 1S1R cell capable of gigabit memory implementation. Furthermore, the demonstration of 1S1R array fabricated completely at room temperature on a plastic substrate highlights the promise of future extremely low-cost flexible nonvolatile memory.
Statistical Study of RRAM MLC SET Variability Induced by Filament Morphology
(2017-01-01)
Hsu, Chung-Wei
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Zheng, Xin
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Wu, Yi
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Hou, Tuo-Hung
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Wong, H. -S. Philip
This paper establishes the correlation between RRAM multilevel-cell (MLC) stochastic SET variability and random telegraph noise (RTN). We show that a smaller diameter (d(D)) of locally connecting/rupturing conductive filament (CF) and larger distance of gap (d(G)) between CF and electrode demonstrate both steeper Weibull slope beta with a relaxed SET-disturb margin by 0.4 V and 36x improvement in RTN robustness. This is achieved by lower current compliances (I-COMP) of 100 mu A and larger RESET stopping voltage (V-RESET) of -4.5 V for smaller dD and larger dG with leaving less residual oxygen vacancies (V-o(+2)) in the gap region. Results from the Kinetic Monte Carlo (KMC) modeling also support these findings.