Browsing by Author "Hsu, HJ"

Now showing 1 - 9 of 9

An incremental analysis to workflow specifications
(2005)
Hsu, HJ
;
Yang, DL
;
Wang, FJ
;
資訊工程學系
;
Department of Computer Science
Workflow management technology helps modulizing and controlling complex business processes within an enterprise. Generally speaking, a workflow management system (WfMS) is composed of two primary components, a design environment and a run-time system. Structural, timing and resource verifications of a workflow specification are required to help assure the correctness of the specified system. In this paper we address an incremental methodology to analyze resource consistency and timing constraints after each editing activity of a workflow specification and to provide proper feedbacks to designer or maintainer of the workflow specification.
Constructing an EJB application in a WFMS
(2002)
Wang, JW
;
Lin, TC
;
Hsu, HJ
;
Wang, FJ
;
資訊工程學系
A workflow system provides enterprises the automatic and paperless process management. The idea of Enterprise JavaBeans (EJB) is to utilize components from various vendors to construct an application, which has the characteristics of scalability, security, distributed, and fast development. In the paper, an EJB module and the enterprise beans are implemented. Workflow designer may use this module to invoke the business methods defined in the enterprise bean on the outer application server. The EJB module may facilitate the component development of a workflow system, and reuse the existing components to fulfill the function needed.
FPGA realization of space-vector PWM control IC for three-phase PWM inverters
(1997-11-01)
Tzou, YY
;
Hsu, HJ
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a new circuit realization of the space-vector pulse-width modulation (SVPWM) strategy. An SVPWM control integrated circuit (IC) has been developed using the state-of-the-art field-programmable gate array (FPGA) technology. The proposed SVPWM control scheme can be realized using only a single FPGA (XC4010) from Xilinx, Inc. The output fundamental frequency can be adjusted from 0.094 to 1500 Hz. The pulse-width modulation (PWM) switching frequency can be set from 381 Hz to 48.84 kHz. The delay time for the PWM gating signals is adjustable. This SVPWM IC can also be included in the digital current control loop for stator current regulation. The designed SVPWM IC can be incorporated with a digital signal processor (DSP) to provide a simple and effective solution for high-performance ac drives. Simulation and experimental results are given to verify the implemented SVPWM control IC.
FPGA realization of space-vector PWM control IC for three-phase PWM inverters
(1997-11-01)
Tzou, YY
;
Hsu, HJ
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a new circuit realization of the space-vector pulse-width modulation (SVPWM) strategy. An SVPWM control integrated circuit (IC) has been developed using the state-of-the-art field-programmable gate array (FPGA) technology. The proposed SVPWM control scheme can be realized using only a single FPGA (XC4010) from Xilinx, Inc. The output fundamental frequency can be adjusted from 0.094 to 1500 Hz. The pulse-width modulation (PWM) switching frequency can be set from 381 Hz to 48.84 kHz. The delay time for the PWM gating signals is adjustable. This SVPWM IC can also be included in the digital current control loop for stator current regulation. The designed SVPWM IC can be incorporated with a digital signal processor (DSP) to provide a simple and effective solution for high-performance ac drives. Simulation and experimental results are given to verify the implemented SVPWM control IC.
FPGA-based SVPWM control IC for 3-phase PWM inverters
(1996)
Tzou, YY
;
Hsu, HJ
;
Kuo, TS
;
交大名義發表
;
電控工程研究所
This paper presents a new circuit realization of the space vector pulsewidth modulation (SVPWM) strategy. A SVPWM control IC has been developed using the state of art field programmable gate array (FPGA) technology. Two RAM-based FPGA, XC4003 and XC4010, from the Xilink Inc. was used for the implementation of the SVPWM IC. This SVPWM IC can also be included in the digital current control loop for stator current regulation. The designed SVPWM IC can be incorporated with a digital signal processor (DSP) to provide a total solution for high-performance ac drives. Simulation and experimental results are given to verify the implemented SVPWM control IC.
Intention scheduling for BDI Agent Systems
(2005)
Lin, ZN
;
Hsu, HJ
;
Wang, FJ
;
資訊工程學系
;
Department of Computer Science
BDI is one of the models in Agent Systems. Currently, most of BDI agents' researches are focused on the ability for agents to dynamically select plans to achieve a goal. There are fewer discussions on Intention Scheduling, the order in which the selected plans are executed Agents must adapt to dynamical and unpredictable changes. Without a proper scheduling scheme, an agent may repeat unnecessary works, waste valuable resource or even jail the users' expect altogether. In this paper, we present an effective intention-scheduling scheme in BDI reasoning process, to make BDI agents more efficient and suitable for execution.
Intention scheduling for BDI agent systems
(2005-01-01)
Yan, SB
;
Lin, ZN
;
Hsu, HJ
;
Wang, FJ
;
資訊工程學系
BDI is one of the models in Agent Systems. Currently, most of BDI agents' researches are focused on,the ability for agents to dynamically select plans to achieve a goal. There are fewer discussions on Intention Scheduling, the order in which the selected plans are executed. Agents must adapt to dynamical and unpredictable changes. Without a proper scheduling scheme, an agent may repeat unnecessary works, waste valuable resource or even fail the users' expect altogether. In this paper, we present an effective intention-scheduling scheme in BDI reasoning process.
Optimal frame memory and data transfer scheme for MPEG-4 shape coding
(2003)
Lee, KB
;
Chang, NYC
;
Chin, HY
;
Hsu, HJ
;
Jen, CW
An optimal frame memory and data transfer scheme is proposed for MPEG-4 shape coding in embedded system. Based on the inherent property of shape information, the binary alpha blocks are losslessly compressed with a fixed 50% compression ratio and can be randomly accessed. Therefore the size of frame memory can be reduced to 50% with a small index table (2.73% similar to 5.08% of the original frame memory size), and the number of memory reference can be reduced to 56.25%. The data transfer scheme combines the run length coding and addressing mode to reduce data transfer time to 9.39%.
Window-based interactive digital control development system using digital signal processors
(1996)
Tzou, YY
;
Lu, FT
;
Yen, WH
;
Hsu, HJ
;
電控工程研究所