Browsing by Author "Hsu, Heng-Shou"

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Accurate Performance Evaluation of HEMT Devices for High-Speed Logic Applications through Rigorous Device Modelling Technique
(2007)
Hsu, Heng-Tung
;
Chang, Chia-Yuan
;
Hsu, Heng-Shou
;
Chang, Edward Yi
;
材料科學與工程學系
Tremendous progress has been made recently in the research of novel nanotechnology for future nano-electronic applications. Among all the possible technologies, III-V FETs particularly the heterostructure High Electron Mobility Transistors (HEMT) have demonstrated promising results to be the future device technology for high-speed logic applications. Precise evaluation of the delay performance for HEMT requires highly accurate intrinsic device models extracted from available measurements. In this paper, a rigorous device modelling technique based on 3-D full wave electromagnetic analysis of the device structure is presented. This technique is efficient and accurate, and the determined equivalent circuit model fits the measured S-parameter very well within the frequency range of interest.
Evaluation of RF and logic performance for 80 nm InAs/InGaAs composite channel HEMTs using gate sinking technology
(2007)
Kuo, Chien-I
;
Hsu, Heng-Tung
;
Chang, Chia-Yuan
;
Chang, Edward Yi
;
Hsu, Heng-Shou
80-nm-gate In(0.7)Ga(0.3)As/InAs/In(0.7)Ga(0.3)As composite channel high-electron mobility transistors (HEMTs) fabricated using platinum (Pt) buried gate as the Schottky contact metal were evaluated for RF and logic application. After gate sinking at the 250 degrees C for 3 minutes, the device exhibited a high g. value of 1590mS/mm at V(d) = 0.5V and the current gain cutoff frequency f(T) was measured to be 494 GHz. The intrinsic gate delay time was calculated to be 0.78 psee at supply voltage of 0.6 V. This is the highest f(T) achieved for 80 nm gate length HEMT devices. These superior performances are attributed to the reduction of distance between. gate and channel, and the reduction of parasitic gate capacitances during gate-sinking process.
Reduction of current mismatching in the switches-in-source CMOS charge pump
(2013-12-01)
Shiau, Miin-Shyue
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Hsu, Heng-Shou
;
Cheng, Ching-Hwa
;
Weng, Hsiu-Hua
;
Wu, Hong-Chong
In this paper, the charge pump (CP) based on a switches-in-source architecture is to be improved by gain-boosting amplifiers for phase-locked loops (PLLs). In our design, two differential amplifiers were employed in this CP to reduce the effect of the channel length modulation in MOS transistors. As a result, the up and down currents will be rather independent of the output voltage transformed by the capacitive low pass filter (LPF). This circuit was implemented using TSMC 0.18-mu m CMOS technology and was investigated at a power supply of 1.8 V. The measured mismatch was less than 1% for the output voltage ranging from 0.4 to 1.4 V. This result is lower than that of the dynamic current-matching CP with feedback tuning on the same architecture. A comparison will be presented and discussed. (C) 2013 Elsevier Ltd. All rights reserved.
Single-pole Double-throw Switch Using Stacked-FET Configuration at Millimeter Wave Frequencies
(2018-01-01)
Mei, Peng-, I
;
Wu, Guan-Wei
;
Hsu, Heng-Shou
;
Huang, Ting-Jui
;
Tsao, Yi-Fan
In this paper, we present single-pole double-throw (SPDT) switch at Ka-band for phased array front-end applications. The proposed switch composed of three shunt arms and a quarter-wave length impedance transformer in series on each branch. The stacked-FET configuration was adopted to enhance the power handling capability. Implemented with 0.15um GaAs pHEMT technology by WIN Semiconductor, the overall chip size was 2 mm by 1 mm. The measured insertion loss was less than 3 dB with better than 25 dB isolation from 15 GHz to 35 GHz. The proposed configuration also featured an input 1 dB compression point of 26 dBm.
V-Band Flip-Chip Assembled Gain Block Using In(0.6)Ga(0.4)As Metamorphic High-Electron-Mobility Transistor Technology
(2011-10-01)
Chiang, Che-Yang
;
Hsu, Heng-Tung
;
Wang, Chin-Te
;
Kuo, Chien-I
;
Hsu, Heng-Shou
This study fabricated a 150 nm In(0.6)Ga(0.4)As metamorphic high-electron-mobility transistor (mHEMT) device with flip-chip packaging. The packaged device exhibited favorable DC characteristics with I(DS) = 350 mA/mm and a transconductance of 600 mS/mm at V(DS) = 0.5V. A maximum available gain (MAG) of 6.5 dB at 60 GHz was achieved with 10 mW DC power consumption. A two-stage gain block was designed and fabricated. The gain block exhibited a small signal gain of 9 dB at 60 GHz with only 20 mW DC power consumption. Such superior performance is comparable to the mainstream submicron complimentary metal-oxide-semiconductor (CMOS) technology with lower power consumption. (C) 2011 The Japan Society of Applied Physics
V-Band Flip-Chip Assembled Gain Block Using In0.6Ga0.4As Metamorphic High-Electron-Mobility Transistor Technology
(2011-10-01)
Chiang, Che-Yang
;
Hsu, Heng-Tung
;
Wang, Chin-Te
;
Kuo, Chien-I
;
Hsu, Heng-Shou
This study fabricated a 150 nm In0.6Ga0.4As metamorphic high-electron-mobility transistor (mHEMT) device with flip-chip packaging. The packaged device exhibited favorable DC characteristics with I-DS = 350 mA/mm and a transconductance of 600 mS/mm at V-DS = 0.5V. A maximum available gain (MAG) of 6.5 dB at 60 GHz was achieved with 10 mW DC power consumption. A two-stage gain block was designed and fabricated. The gain block exhibited a small signal gain of 9 dB at 60 GHz with only 20 mW DC power consumption. Such superior performance is comparable to the mainstream submicron complimentary metal-oxide-semiconductor (CMOS) technology with lower power consumption. (C) 2011 The Japan Society of Applied Physics