Browsing by Author "Hsu, Hisang-Hua"

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Demonstrating 1 nm-oxide-equivalent-thickness La2O3 and HfO2 multi-layer composite oxides on In0.53Ga0.47As MOS capacitor
(2016-01-08)
Wu, Wen-Hao
;
Lin, Yueh-Chin
;
Hou, Tzu-Ching
;
Lin, Tai-Wei
;
Hsu, Hisang-Hua
The use of a high k composite dielectric composed of La2O3 and HfO2 layers as the gate dielectric for In0.53Ga0.47As MOS application is proposed. Two multi-layer structures of La2O3 (1 nm)/HfO2 (1 nm) and La2O3 (0.5 nm)/HfO2 (0.5 nm) were deposited and annealed at 450 and 500 degrees C for device performance comparison. X-ray photoelectron spectroscopy, TEM and C-V measurements were used for the interface analysis between the oxide and the semiconductor. Finally, a 1 nm equivalent-oxide-thickness dielectric with small hysteresis of 88 mV and D-it of 1.9 x 10(12) cm(-2) eV(-1) was achieved for six layers of an La2O3 (0.5 nm)/HfO2 (0.5 nm) composite oxide structure on an In0.53Ga0.47As MOS capacitor with a post-deposition annealing temperature of 450 degrees C.
Evaluation of a 100-nm Gate Length E-Mode InAs High Electron Mobility Transistor With Ti/Pt/Au Ohmic Contacts and Mesa Sidewall Channel Etch for High-Speed and Low-Power Logic Applications
(2018-01-01)
Yao, Jing-Neng
;
Lin, Yueh-Chin
;
Hsu, Heng-Tung
;
Yang, Kai-Chun
;
Hsu, Hisang-Hua
In this paper, a 100-nm gate length InAs high electron mobility transistor (HEMT) with non-alloyed Ti/Pt/Au ohmic contacts and mesa sidewall channel etch was investigated for high-speed and low-power logic applications. The device exhibited a low subthreshold swing (SS) of 63.3 mV/decade, a drain induced barrier lowering value of 23.3 mV/V, an I-on/I-off ratio of 1.34 x 10(4), a G(m,max)/SS ratio of 27.6, a current gain cut-off frequency of 439 GHz with a gate delay time of 0.36 ps, and an off-state gate leakage current of less than 1.6 x 10(-5) A/mm at V-DS = 0.5 V. These results demonstrated that the presence of non-annealed ohmic contacts with mesa sidewall etch process allowed the fabrication of InAs HEMTs with excellent electrical characteristics for high-speed and low-power logic applications.
Improved linearity and reliability in GaN metal-oxide-semiconductor high-electron-mobility transistors using nanolaminate La2O3/SiO2 gate dielectric
(2016-04)
Hsu, Ching-Hsiang
;
Shih, Wang-Cheng
;
Lin, Yueh-Chin
;
Hsu, Heng-Tung
;
Hsu, Hisang-Hua
Improved device performance to enable high-linearity power applications has been discussed in this study. We have compared the La2O3/SiO2 AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with other La2O3-based (La2O3/HfO2, La2O3/CeO2 and single La2O3) MOS-HEMTs. It was found that forming lanthanum silicate films can not only improve the dielectric quality but also can improve the device characteristics. The improved gate insulation, reliability, and linearity of the 8 nm La2O3/SiO2 MOS-HEMT were demonstrated. (C) 2016 The Japan Society of Applied Physics
Improved linearity and reliability in GaN metal-oxide-semiconductor high-electron-mobility transistors using nanolaminate La2O3/SiO2 gate dielectric
(2016-04-01)
Hsu, Ching-Hsiang
;
Shih, Wang-Cheng
;
Lin, Yueh-Chin
;
Hsu, Heng-Tung
;
Hsu, Hisang-Hua
Improved device performance to enable high-linearity power applications has been discussed in this study. We have compared the La2O3/SiO2 AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with other La2O3-based (La2O3/HfO2, La2O3/CeO2 and single La2O3) MOS-HEMTs. It was found that forming lanthanum silicate films can not only improve the dielectric quality but also can improve the device characteristics. The improved gate insulation, reliability, and linearity of the 8 nm La2O3/SiO2 MOS-HEMT were demonstrated. (C) 2016 The Japan Society of Applied Physics