Browsing by Author "Hsu, Hsin-Chyh"

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Automation of synchronous bias transmission line pulsing system
(2007)
Chang, Bor-Wei
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Hsu, Hsin-Chyh
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Ker, Ming-Dou
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Synchronous Bias Transmission Line Pulsing (SB-TLP) system is able to provide a synchronous bias voltage to transmission line Pulse. It\'s a more useful test bench to evaluate actual circuit characteristics of electrostatic discharge (ESD) protection design with gate-driven mechanism than traditional Transmission Line Pulsing (TLP) system. It\'s important to set up an automatic SB-TLP system and be able to immediately analyze measured data which is more convenient to engineers. All of the instruments are controlled by a software written in LabVIEW environment to create a smart and friendly test workbench.
Dummy-gate structure to improve ESD robustness in a fully-salicided 130-nm CMOS technology without using extra salicide-bloc king mask
(2006)
Hsu, Hsin-Chyh
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Ker, Ming-Dou
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電機學院
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College of Electrical and Computer Engineering
NMOS with dummy-gate structure is proposed to significantly improve electrostatic discharge (ESD) robustness in a fully-salicided CMOS technology. By using this structure, ESD current is discharged far away from the salicided surface channel of NMOS, therefore the NMOS can sustain a much higher ESD level. The HBM (MM) ESD robustness of the NMOS with dummy-gate structure (W/L = 480 mu m/0.18 mu m) has been successfully improved from 0.5 kV (125 V) to 1.5 W (325 V) in a 130-nm fully-salicided CMOS process. Under the same layout area of the gate-grounded NMOS (ggNMOS), HBM (MM) ESD level can be improved over 300% (260%) by the proposed dummy-gate structure. The proposed dummy-gate structure is fully process compatible to general salicided CMOS processes without additional mask which is very cost-efficient for application in the IC products.
The impact of inner pickup on ESD robustness of multi-finger NMOS in nanoscale CMOS technology
(2006)
Ker, Ming-Dou
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Hsu, Hsin-Chyh
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電機學院
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College of Electrical and Computer Engineering
The impact of pickup structure on ESD robustness of multi-finger MOSFET devices in the nanoscale CMOS process is investigated in this work with 1.2-V and 2.5-V devices in a 130-nm CMOS process. The multi-finger MOSFET device without the pickup structure inserted into its source region can sustain a much higher ESD level and more compact layout area for I/O cells.