Browsing by Author "Hsu, Hsin-Wu"

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Area-I/O RDL Routing for Chip-Package Codesign Considering Regional Assignment
(2010-01-01)
Lin, Kun-Sheng
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Hsu, Hsin-Wu
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Lee, Ren-Jie
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Chen, Hung-Ming
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電子工程學系及電子研究所
Flip-Chip package provides high density I/Os and better performance in package size, signal/power integrety, and wirelength. Routing on its Re-Distribution Layer (RDL) is one of the most difficult stage in Flip-Chip packaging due to the increasing number of I/Os in modern VLSI designs. Area I/O can shorten the signal path and further increases the I/O density, but the design complexity is also higher. The Area I/O RDL routing problem is introduced in this paper, considering wirelength minimization and chip-package codesign. The proposed algorithm effectively solves the problem. 100% routability is guaranteed, from block ports to I/O pads and from I/O pads to bump pads. The authors propose the concept of regional assignment to evaluate the skew between bumps and balls. It leads the nets to route within neighbor sectors rather than the opposite sector. The experimental results, on 7 industrial designs, show that the router greatly minimizes bump-ball skew compared with [12], with reasonable extra wirelength.
Board- and Chip-Aware Package Wire Planning
(2013-08-01)
Lee, Ren-Jie
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Hsu, Hsin-Wu
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Chen, Hung-Ming
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The slow turnaround between design, package, and system houses has been one of the primary concerns in the semiconductor business. There is a serious lag in the development time of the systems due to time-consuming interface design between the chip, package, and board. In order to enable chip-package-board codesign to speed up the design process, we propose an approach to address this issue by efficiently planning wires for board and chip design awareness, which includes the package pin-out designation and the corresponding wire planning in package and board. We model the problem as an interval intersection problem. Because of the special need in pin-out rules, an algorithm to resolve the problem is developed. We then use some optimization techniques to further improve objectives such as global wire congestion and length deviation. Our results show that a very efficient estimation can be made considering those important objectives, and package congestion can be successfully mitigated.
On Effective Flip-Chip Routing via Pseudo Single Redistribution Layer
(2012-01-01)
Hsu, Hsin-Wu
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Chen, Meng-Ling
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Chen, Hung-Ming
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Li, Hung-Chun
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Chen, Shi-Hao
Due to the advantage of flip-chip design in power distribution but controversial peripheral 10 placement in lower design cost, redistribution layer (RDL) is usually used for such interconnection. Sometimes RDL is so congested that the capacity for routing is insufficient. Routing therefore cannot be completed within a single layer even for manual routing. Although [2] proposed a routing algorithm that uses two layers of RDLs, but in practice the required routing area is a little more than one layer. We overcome this problem by adopting the concept of pseudo single-layer. With the heuristics for routing on mapped channels and observations on staggered pins to relieve vertical constraints, the area of 2-layer routing can be minimized and the routability is 100%. Comparisons of routing results between manual design, the commercial tool, and the proposed method are presented. We have shown the effectiveness on a real industrial case: it originally required fully manual design, the proposed method can finish RDL routing automatically and effectively.