Browsing by Author "Hsu, JC"

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A machine learning approach for acquiring descriptive classification rules of shape contours
(1997-02-01)
Hsu, JC
;
Hwang, SY
;
資訊工程學系
;
Department of Computer Science
We devise a method to generate descriptive classification rules of shape contours by using inductive learning. The classification rules are represented in the form of logic programs. We first transform input objects from pixel representation into predicate representation. The transformation consists of preprocessing, feature extraction and symbolic transformation. We then use FOIL which is an indictive logic programming system to produce classification rules. Experiments on two sets of data were performed to justify our proposed method. Copyright (C) 1997 pattern Recognition Society.
A machine learning approach for acquiring descriptive classification rules of shape contours
(1997-02-01)
Hsu, JC
;
Hwang, SY
;
資訊工程學系
;
Department of Computer Science
We devise a method to generate descriptive classification rules of shape contours by using inductive learning. The classification rules are represented in the form of logic programs. We first transform input objects from pixel representation into predicate representation. The transformation consists of preprocessing, feature extraction and symbolic transformation. We then use FOIL which is an indictive logic programming system to produce classification rules. Experiments on two sets of data were performed to justify our proposed method. Copyright (C) 1997 pattern Recognition Society.
A spread spectrum clock generator for SATA-II
(2005)
Chen, WT
;
Hsu, JC
;
Lune, HW
;
Su, CC
;
電控工程研究所
In this paper, we proposed a spread spectrum clock generator (SSCG) for the Serial AT Attachment Generation 2 (SATA-II). We use a fractional-N PLL to accomplish the spread spectrum function. The SSCG integrates a conventional PLL, a digital 3(rd) order MASH 1-1-1 delta-sigma modulator and an address generator. The SSCG generates clocks at 1.5 GHz, a 5000 ppm down spread with a triangular waveform frequency modulation of 33 KHz. The circuit has been simulated in 0.18 um CMOS technology. The non spread spectrum clocking has a jitter of 80 ps and the peak amplitude reduction is 23.44 dBm in spread spectrum mode. The power dissipation from a 1.8 V supply is 55 mW.