Browsing by Author "Hsu, JJ"

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Effect of Zr/Ti ratios on characterization of Pb(ZrxTi1-x)O-3 thin films on Al2O3 buffered Si for one-transistor memory applications
(2003-03-01)
Sun, CL
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Hsu, JJ
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Chen, SY
;
Chin, A
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材料科學與工程學系
Pb(ZrxTi1-)O-3 (PZT) thin films have been prepared on Al2O3/Si and PbTiO3/Al2O3/Si substrates, respectively. On Al2O3/Si substrates, Ti-rich PZT thin films had lower perovskite transformation temperatures than those of Zr-rich PZT films. Therefore, PbTiO3 was used as the seeding layer on Al2O3/Si to form a PbTiO3/Al2O3/Si substrate. The threshold voltage shift of a PZT(53/ 47)/PbTiO3/Al2O3/Si capacitor reaches 9 V with +/-10 V writing voltages, which is much larger than the 2 V of the PZT(0/100)/PbTiO3/Al2O3/Si capacitor. Different memory mechanisms in the capacitance-voltage characteristics of capacitors were further examined and discussed in this paper. (C) 2003 The Electrochemical Society.
Forming gas annealing on physical characteristics and electrical properties of Sr0.8Bi2Ta2O9/Al2O3/Si capacitors
(2003-08-01)
Lan, BC
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Hsu, JJ
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Chen, SY
;
Bow, JS
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材料科學與工程學系
Sr0.8Bi2Ta2O9 (SBT) ferroelectric film constructed on Al2O3/Si to form metal-ferroelectric-insulator-semiconductor (MFIS) was prepared to study the degradation behavior of SBT films under forming gas annealing (FGA). Although the diffusion of hydrogen ions has been detected during FGA treatment, no significant differences in the microstructure and crystalline phase are observed for the SBT film compared to that without FGA treatment. However, the diffusion of hydrogen ions leads to the rapid decrease in the dielectric constant but shows no apparent influence on the memory window of Sr0.8Bi2Ta2O9/Al2O3/Si capacitors. In addition, it was found that FGA shows a positive effect on the leakage current of MFIS in contrast to that of metal/ferroelectric/metal structure. The leakage current density of MFIS dramatically decreases as much as two orders of magnitude after FGA at 500degreesC compared to that without FGA treatment that was attributed to the reduced defects at the interface of Al2O3/Si. (C) 2003 American Institute of Physics.
Interfacial microstructure and electrical properties of PT/Al2O3/Si annealed at high temperatures
(2004-11-15)
Chen, SY
;
Hsiao, CS
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Hsu, JJ
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材料科學與工程學系
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Department of Materials Science and Engineering
Pb1+xTiO3 (PT) thin films were deposited on Al2O3(10 nm)/Si using lead acetate trihydrate and titanium isopropoxide with the addition of glycerol (GL) chelating agent as precursors. It was found that perovskite PT phase can be well crystallized at a lower temperature of 600 degreesC and excellent memory properties are obtained. However, with increasing annealing temperature above 700 degreesC, charge-injection mode instead of ferroelectric behavior was detected. Cross-sectional TEM results illustrate that with an increase of annealing temperature and Pb content in the PT films, diffusion envelops and even composition separations were detected in the interface of PT/Al2O3/Si. It was believed that the degradation in the ferroelectric memory properties is strongly related to the change of microstructure and composition in the interface of PT/Al2O3/Si. (C) 2004 Elsevier B.V. All rights reserved.
ULSI multi-layer thin film passivation processes for improving cache memory performance
(1998)
Lin, CF
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Tseng, WT
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Feng, MS
;
Chang, YF
;
Hsu, JJ
A multi-layer thin film structure based on PECVD SiO2/SiNx layers are deposited and characterized, in order to improve and optimize the electrical performance and hot carrier reliability of poly load resistors in 4-transistor (4-T) cache Static Random Access Memory (SRAM) devices. SiH4/N2O gas mixtures are utilized as precursors for oxide CVD process. Higher SiH4/N2O flow rate ratios render the resulting oxide films more silicon-rich, as manifested by their higher refractive index (R.I.) and BOE etch rates. These modifications in film characteristics also correspond to enhanced resistance of poly load resistor and lower % hot-carrier linear drain current (I-dlin) degradation. An increase in R.I. from 1.46 to 1.60 translates to a rise in resistance of poly load resistor from 98 Ga to 225 G Omega and a fall in I-dlin from 5.8 % to 4.5 %. Further improvement in device performance can be fulfilled by modifying the stoichiometry of the overlying nitride passivation layer. This is achieved by increasing bias power while reducing SiH4/NH3 gas flow rate ratio during the PECVD nitride deposition process. The nitride films thus deposited contain lower SI-H bond density, and exhibit lower BOE etch rates and compressive stress. Passivation structures based on the combination of a high RI SRO with a tow Si-H content nitride layers yield the most promising device performance and reliability. Water and hydrogen diffusion to the poly gate and load resistor are both held responsible for device degradation.