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Browsing by Author "Hsu, Jen-Chien"

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    BIST for measuring clock jitter of charge-pump phase-locked loops
    (2008-02-01)
    Hsu, Jen-Chien
    ;
    Su, Chauchin
    ;
    電控工程研究所
    ;
    Institute of Electrical and Control Engineering
    This paper presents a built-in self-test (BIST) circuit that measures the clock jitter of the charge-pump phase-locked loops (PLLs). The jitter-measurement structure is based on a novel time-to-digital converter (TDC) which has a high resolution. A small area overhead is also achieved using the voltage-controlled oscillator and the loop filter of the PLL under test as parts of the TDC. The experiment result shows that the resolution is about 1 ps and that the measurement error is smaller than 20%.