Browsing by Author "Hsu, Jen-Yuan"

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A Lattice-Reduction Aided List Demapper for Coded MIMO Receiver
(2013)
Hsieh, Tung-Jung
;
Sheen, Wern-Ho
;
Chen, Sin-Horng
;
Hsu, Jen-Yuan
;
資訊工程學系
The max-log list demapper has been widely employed in the implementations of a coded multiple-input multiple-output (MIMO) receiver, where only a candidate-list of signal vectors is examined in the likelihood-ratio calculation to reduce complexity. Traditionally, the candidate-list is generated in the original-lattice domain which, unfortunately, results in a severe degradation in the performance of demapper if the channel is in ill-condition. In this paper, a new lattice-reduction aided max-log list demapper is proposed in which the candidate-list is generated after a successive cancellation of multi-layer interference in the lattice-reduced domain. Thanks to the newly designed metrics and search algorithms for the generation of the candidate-list, the proposed demapper provides significant gains over the existing methods, especially for the cases with a small list size and/or under a spatially-correlated channel.
A Lattice-Reduction Aided Max-Log List Demapper for Iterative Coded MIMO Receiver
(2014-01-01)
Hsieh, Tung-Jung
;
Sheen, Wern-Ho
;
Chen, Sin-Horng
;
Hsu, Jen-Yuan
;
資訊工程學系
The max-log list demapper has been widely employed in the implementation of a coded multiple-input multiple-output (MIMO) receiver, where only a candidate-list of signal vectors is examined in the likelihood-ratio calculation to reduce complexity. Traditionally, the candidate-list is generated in the original-lattice domain which, unfortunately, results in a severe degradation in the performance of demapper if the channel is in ill-condition. In this paper, a new lattice-reduction aided max-log list demapper is proposed for iterative receivers in which the candidate-list is generated after a successive cancellation of multi-layer interference in the lattice-reduced domain. Thanks to the newly designed metric and search algorithm for the generation of the candidate-list, the proposed demapper provides significant gains over the existing methods, especially for the cases with a small list size and/or under a spatially-correlated channel. The prior information coming out of the decoder is also exploited to lower the complexity of the demapper.
An SVD-aided List Demapper for Iterative Coded-MIMO Receivers
(2014-01-01)
Hsieh, Tung-Jung
;
Sheen, Wern-Ho
;
Chen, Sin-Horng
;
Hsu, Jen-Yuan
;
資訊工程學系
The list demapper has been widely implemented in a coded multiple-input multiple-output (MIMO) receiver, where only a part of total signal vectors are examined in the calculation of likelihood ratio for low complexity. Generally, the list is generated either in the original or the lattice-reduced domain. In the latter, thanks to the operation of lattice reduction (LR), a better-conditioned MIMO channel is obtained, and the adverse effect of noise enhancement is mitigated in the generation of list and thus can achieve a better performance. In this paper, a new singular-value-decomposition (SVD)-aided list demapper is proposed for the iterative coded-MIMO receiver. With SVD, the layer interference incurred in the operation of LR can be avoided, and that renders the SVD-aided list demapper a lower complexity. Computer simulations have confirmed that the proposed demapper has better performance-complexity tradeoffs as compared to the best-performed LR-aided methods in the literature.
Extrinsic Data Compression Method for Double-Binary Turbo Codes
(2012)
Ou-Yang, Yi-Huan
;
Kao, Chien-Yu
;
Hsu, Jen-Yuan
;
Ting, Pang-An
;
Lee, Chen-Yi
This paper presents an extrinsic data compression method for double-binary turbo codes. Frame and extrinsic data memory occupy more area in turbo decoder implementations with the frame size increasing. Besides, non-binary turbo codes have much more extrinsic memory usage than single-binary turbo codes. This proposed compression method utilizes an operation in radix-4 single-binary turbo decoder and also can simplify the integration of single and double-binary turbo decoders in hardware implementations. It can reduce one-third of extrinsic memory size, about 15% of total memory usage. Simulation results show that this method only causes 0.2dB performance loss when bit error rate is equal to 10-5 with slight hardware increment.