Browsing by Author "Hsu, Jenchien"

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A digital BIST methodology for spread spectrum clock generators
(2006)
Chou, Maohsuan
;
Hsu, Jenchien
;
Su, Chauchin
;
電控工程研究所
;
Institute of Electrical and Control Engineering
In this paper, a built-in-self-test methodology for spread-spectrum clock generators is presented. It utilizes a multi-phase phase detector to detect the linearity of the frequency variation and the short-term jitter. The methodology is analyzed and simulated. As an all digital design, the hardware overhead is very small.
A digital BIST methodology for spread spectrum clock generators0
(2006)
Chou, Maohsuan
;
Hsu, Jenchien
;
Su, Chauchin
;
電控工程研究所
;
Institute of Electrical and Control Engineering
In this paper, a built-in-self-test methodology for spread-spectrum clock generators is presented. It utilizes a multi-phase phase detector to detect the linearity of the frequency variation and the short-term jitter. The methodology is analyzed and simulated. As an all digital design, the hardware overhead is very small.
Built-in jitter measurement methodology for spread-spectrum clock generators
(2008)
Hsu, Jenchien
;
Chou, Maohsuan
;
Su, Chauchin
;
電控工程研究所
;
Institute of Electrical and Control Engineering
In this paper, a built-in-self-test methodology for measuring frequency deviation and jitter of spread-spectrum clock generators is presented. It utilizes a phase detector to detect the clock phase of spread spectrum clock (SSC) and then measure the jitter by filtering out the low frequency component of the clock phase. Frequency of spread-spectrum clock can also be obtained by filtering out the high frequency component of the signal. The methodology is analyzed and verified with chip implementation and measurement. As an all digital design, the hardware overhead is very low.
Timing Jitter and Modulation Profile Extraction for Spread-Spectrum Clocks
(2010-04-01)
Hsu, Jenchien
;
Su, Chauchin
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a built-in jitter measurement approach for measuring the timing jitter of spread-spectrum clocks (SSCs) and a jitter estimation method for validating the approach. Because of the lack of dedicated measurement instruments for SSC timing jitter measurement, the jitter estimation method is proposed to correlate SSC and non-SSC jitter. A 1.2-GHz eight-phase SSC generator with the jitter measurement circuit is designed and fabricated using the 0.18-mu m complementary metal-oxide semiconductor technology. The measured results are validated by the proposed estimation method, which is the key contribution of this paper. The experimental results show that the proposed built-in measurement approach has an error of less than 0.0026 UI.