Browsing by Author "Hsu, Li-Chung"

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Development of CpG-Oligodeoxynucleotides for Effective Activation of Rabbit TLR9 Mediated Immune Responses
(2014-09-30)
Chuang, Tsung-Hsien
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Lai, Chao-Yang
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Tseng, Ping-Hui
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Yuan, Chiun-Jye
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Hsu, Li-Chung
CpG-oligodeoxynucleotides (CpG-ODN) are potent immune stimuli being developed for use as adjuvants in different species. Toll-like receptor 9 (TLR9) is the cellular receptor for CpG-ODN in mammalian cells. The CpG-ODN with 18-24 deoxynucleotides that are in current use for human and mouse cells, however, have low activity with rabbit TLR9. Using a cell-based activation assay, we developed a type of CpG-ODN containing a GACGTT or AACGTT motif in 12 phosphorothioate-modified deoxynucleotides with potent stimulatory activity for rabbit TLR9. The developed CpG-ODN have higher activities than other developed CpG-ODN in eliciting antigen-nonspecific immune responses in rabbit splenocytes. When mixed with an NJ85 peptide derived from rabbit hemorrhagic disease virus, they had potent activities to boost an antigen-specific T cell activation and antibody production in rabbits. Compared to Freund\'s adjuvant, the developed CpG-ODN are capable of boosting a potent and less toxic antibody response. The results of this study suggest that both the choice of CpG-motif and its length are important factors for CpG-ODN to effectively activate rabbit TLR9 mediated immune responses.
On optimizing scan testing power and routing cost in scan chain design
(2006)
Hsu, Li-Chung
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Chen, Hung-Ming
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC design, circuit testability becomes one of the most challenging works. Without careful design in scan cell placement and chain ordering, circuits consume much more power in test mode operation than that in normal functional mode. This elevated testing power may cause problems including overall yield lost and instant circuit damage. In this paper, we present an approach to simultaneously minimizing power and routing cost in scan chain reordering after cell placement. We formulate the problem as a Traveling Salesman Problem (TSP), different cost evaluation from [3], [5], and apply an efficient heuristic to solve it. The experimental results are encouraging. Compared with a recent result in [3], which uses the approach with clustering overhead, we obtain up to 10% average power saving under the same low routing cost. Furthermore, we obtain 57% routing cost improvement under the same test power consumption in s9234, one of ISCAS\'89 benchmarks. We collaborate multiple scan chains architecture with our methodology and obtain good results as well.
On Reducing Test Power, Volume and Routing Cost by Chain Reordering and Test Compression Techniques
(2010-03-01)
Lin, Chia-Yi
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Hsu, Li-Chung
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Chen, Hung-Ming
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
With the advancement of VLSI manufacturing technology entire electronic systems can be Implemented in a single intergrated circuit Due to the complexity in SoC design. circuit testability becomes one of the most challenging works Without careful planning it Design For Testability (DFT) design, circuits consume mote power in test mode operation than that in normal functional mode This elevated testing power may cause problems including overall yield lost and instant circuit damage In this paper, we present two approaches to minimize scan based DFT power dissipation First methodology Includes routine cost consideration in scan chain reordering after cell placement. while second methodology provides test pattern compression for lower power We formulate the first problem as a Traveling Salesman Problem (TSP). with different cost evaluation from [18],[19] and apply an efficient heuristic to solve it lit the second problem we provide a selective scan chain architecture and perform a simple yet effective encoding scheme for lower scan testing power dissipation The experimental results of ISCAS'89 benchmarks show that the first methodology obtains up to 10% average power saving under the same low routing cost compared with a recent result in [19] The second methodology reduces over 17% of test power compared with filling all don't care (X) bit with 0 in one of ISCAS'89 benchmarks We also provide the integration flow of these two approaches in this paper