Browsing by Author "Hsu, Sheng-Fu"

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Component-level measurement for transient-induced latch-up in CMOS ICs under system-level ESD considerations
(2006-09-01)
Ker, Ming-Dou
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Hsu, Sheng-Fu
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電機學院
;
College of Electrical and Computer Engineering
To accurately evaluate the immunity of CMOS ICs against transient-induced latch-up (TLU) under the system-level electrostatic discharge (ESD) test for electromagnetic compatibility (EMC) regulation, an efficient component-level TLU measurement setup with bipolar (underdamped sinusoidal) trigger is developed in this paper. A current-blocking diode and a current-limiting resistance, which are generally suggested to be used in the TLU measurement setup with bipolar trigger, are investigated for their impacts to both the bipolar trigger waveforms and the TLU immunity of the device under test (DUT). All the experimental results have been successfully verified with device simulation. Finally, a TLU measurement setup without a current-blocking diode but with a small current-limiting resistance, which can accurately evaluate the TLU immunity of CMOS ICs with neither overestimation nor electrical-over-stress damage to the DUT during the TLU test, is suggested. The suggested measurement setup has been verified with silicon-controlled-rectifier test structures and real circuitry (ring oscillator) fabricated in 0.25-mu m CMOS technology.
Dependence of device structures on latchup immunity in a high-voltage 40-V CMOS process with drain-extended MOSFETs
(2007-04-01)
Hsu, Sheng-Fu
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Ker, Ming-Dou
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電機學院
;
College of Electrical and Computer Engineering
The dependence of device structures on latchup immunity in a 0.25-mu m high-voltage (HV) 40-V CMOS process with drain-extended MOS (DEMOS) transistors has been verified with silicon test chips and investigated with device simulation. Layout parameters such as anode-to-cathode spacing and guard ring width are also investigated to find their impacts on latchup immunity. It was demonstrated that the drain-extended NMOS with a specific isolated device structure can greatly enhance the latchup immunity. The proposed test structures and simulation methodologies can be applied to extract safe and compact design rule for latchup prevention of DEMOS transistors in HV CMOS process.
Experimental evaluation and device simulation of device structure influences on latchup immunity in high-voltage 40-V CMOS process
(2006)
Hsu, Sheng-Fu
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Ker, Ming-Dou
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Lin, Geeng-Lih
;
Jou, Yeh-Ning
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電機學院
The dependence of device structures and layout parameters on latchup immunity in high-voltage (HV) 40-V CMOS process have been verified with silicon test chips and investigated with device simulation. It was demonstrated that a specific test structure considering the parasitic silicon controlled rectifier (SCR) resulting from isolated asymmetric HV NMOS and HV PMOS has the best latchup immunity. The test structures and simulation methodology proposed in this work can be applied to extract safe and compact design rule for latchup prevention in HV CMOS process. All the test chips are fabricated in a 0.25-mu m 40-V CMOS technology.
Study of board-level noise filters to prevent transient-induced latchup in CMOS integrated circuits during EMC/ESD test
(2006)
Hsu, Sheng-Fu
;
Ker, Ming-Dou
;
電機學院
;
College of Electrical and Computer Engineering
Different types of board-level noise filters are evaluated for their effectiveness to improve the immunity of CMOS ICs against transient-induced latchup (TLU) under system-level electrostatic discharge (ESD) test. By choosing proper components in each noise filter network, the TLU immunity of CMOS ICs can be greatly improved. All the experimental evaluations have been verified in test chips with the silicon controlled rectifier (SCR) fabricated in a 0.25-mu m CMOS technology. Some of such board-level solutions can be further integrated into the chip design to effectively improve TLU immunity of CMOS IC products.
Transient-induced latchup dependence on power-pin damping frequency and damping factor in CMOS integrated circuits
(2007-08-01)
Hsu, Sheng-Fu
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The bipolar (underdamped sinusoidal) transient noise on power pins of CMOS integrated circuits (ICs) can trigger latchup in CMOS ICs under system-level electrostatic-discharge test. Two dominant parameters of bipolar transient noise-damping frequency and damping factor-strongly depend on system shielding, board-level noise filter, chip-/board-level layout, etc. The transient-induced-latchup (TLU) dependence on power-pin damping frequency and damping factor was characterized by device simulation and verified by experimental measurement. From the simulation results, bipolar-trigger waveforms with damping frequencies of several tens of megahertz can trigger the TLU.most easily. However, TLU is less sensitive to the bipolar-trigger waveforms with an excessively large damping factor or an excessively low/high damping frequency. The simulation results have been experimentally verified with the silicon-controlled-rectifier (SCR) test structures that are fabricated in a 0.25-mu m CMOS technology.