Browsing by Author "Hsu, TH"

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MAC protocols for multi-channel WLANs
(2005-01-01)
Liu, YS
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Hsu, TH
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電信工程研究所
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Institute of Communications Engineering
Wireless local area networks, in which every station can transmit via any one of the available operating channels, but only one channel at a time. are investigated. Two distributed random access protocols are proposed for these WLANs. The CSMA/CA protocol is similar to the IEEE 802.11 standard but with slight modifications for multiple operating channels. The fuzzy logic controlled protocol employs a simple fuzzy logic controller to tune the size of backoff window. Extensive simulations are provided to evaluate the channel utilization, fairness, and responsiveness of these two protocols. Furthermore, the effects of employing RTS/CTS mechanism with both protocols are considered. Finally, performances of these two protocols are also investigated under conditions of burst traffic and noisy channels. Simulation results show that the fuzzy logic controlled protocol is a great improvement of the CSMA/CA protocol.
Novel program versus disturb window characterization for split-gate flash cell
(2005-03-01)
Sung, HC
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Lei, TF
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Hsu, TH
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Kao, YC
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Lin, YT
In this letter, a new methodology for program versus disturb window characterization on split gate Flash cell is presented for the first time. The window can be graphically illustrated in V-wI (word-line)-V-ss (source) domain under a given program current. This method can help us understand quantitatively how the window shifts versus bias conditions and find the optimal program condition. The condition obtained by this method can have the largest tolerance for program, bias variations. This methodology was successfully implemented in 0.18-mum triple self-aligned (SA3) split-gate cell characterization to provide program condition for 32 M products.
Novel single-poly EEPROM with damascene control-gate structure
(2005-10-01)
Sung, HC
;
Lei, TF
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Hsu, TH
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Wang, SW
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Kao, YC
A novel single-poly EEPROM using damascene control gate (CG) structure is presented in this letter. The CG is tungsten (W) line made by a damascene process, and intergate dielectric is Al2O3 grown by atomic layer deposition (ALD). The program and erase mechanism is the same as the one for traditional stacked-gate cell, which uses the channel hot electron injection for programming and Fowler-Nordheim tunneling for channel erasing. With the high dielectric constant (K) property of Al2O3, we can perform the program and erase function with a voltage less than 6.5 V, which can be handled by 3.3 V devices instead of traditional high voltage devices. In the process compatibility aspect, this new cell needs only two extra masking steps over the standard CMOS process, and the high-kappa material is deposited in the back-end metallization steps without the contamination concerns on the front-end process. Therefore, this new technology is suitable for embedded application. In this letter, the good cell performance is demonstrated; such as, fast programming/erasing, good endurance and data retention.