Browsing by Author "Hsu, W. S."

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Effective surface treatments for selective epitaxial SiGe growth in locally strained pMOSFETs
(2007-01-01)
Cheng, P. L.
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Liao, C. I.
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Wu, H. R.
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Chen, Y. C.
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Chien, C. C.
Several dry and wet surface treatment methods are explored for a selective SiGe epitaxial film used to fabricate embedded SiGe pMOSFETs. Pre-clean conditions for the device wafers used in this study were limited by a realistic CMOS process window with tight thermal and chemical budgets due to dopant diffusion and hardmask erosion concerns. The effectiveness of these pre-clean methods is evaluated by SiGe epitaxial film quality and SIMS profiles of key residual contaminants such as C and O at the SiGe-Si substrate interface. As an effective low-temperature dry surface treatment, chemical bake in HCl/H-2 at temperature below 800 degrees C is found to reduce interface C and O peak concentrations by an order of magnitude. Wet clean in multiple cycles of DIW-O-3 (ozonated water), SC1 and diluted HF (DHF) is also presented to prepare epitaxial growth surfaces with accumulated damage and chemical residues from previous process steps. SiGe epitaxial film morphology is also observed to improve by increasing DHF clean time. For further improvement of film quality on the most difficult surfaces, Si seed layer was employed to initiate SiGe film nucleation and yield smooth film growth.
Effectiveness of Si thin buffer layer for selective SiGe epitaxial growth in recessed source and drain for pMOS
(2008-02-15)
Chenga, P. L.
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Liao, C. I.
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Chien, C. C.
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Yang, C. L.
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Ting, S. F.
Locally strained Si technology using embedded SiGe has been used to improve pMOSFET device performance through hole mobility enhancement. Embedded SiGe is achieved by selectively growing epitaxial SiGe film in recessed Si pMOSFET source and drain areas. Prior to selective SiGe epi growth, a thin layer of Si seed was employed to help nucleate following low-temperature selective SiGe epitaxial film in recessed. source and drain areas. In combination with pre-epi wet clean and low-temperature chemical bake, use of Si seed resulted in improved SiGe film morphology and micro-loading effect, and further improved device performance. (c) 2007 Elsevier B.V. All rights reserved.
Nano-roughening for reliable N/MEMS manufacture
(2006)
Yang, Chia-Yeh
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Cheng, Y. T.
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Hsu, W. S.
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents a nano-roughneneing technique to effectively modify bonding surface for ensuring for the continuation of hermetic encapsulation shrinkage from MEMS to NEMS. The roughening is realized via a non-uniform etch characteristic of PR which is etched then utilized as an etching mask for the following silicon etching process. UV adhesive bonding is utilized for the verification of the nano-roughening for NEMS hermetic encapsulation. The average roughnesses of silicon substarte before and after the modification are 0.4nm and 12.4nm respectively. The roughness increase can effectively provide more than 30% bonding strength enhancement and 8% leakage reduction.