Browsing by Author "Hsu, Wan-Ling"

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Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture
(2011-04-01)
Huang, Juinn-Dar
;
Chen, Chia-I
;
Lin, Yen-Ting
;
Hsu, Wan-Ling
;
電子工程學系及電子研究所
In deep-submicron era, wire delay is becoming a bottleneck while pursuing even higher system clock speed. Several distributed register (DR) architectures have been proposed to cope with this problem by keeping most wires local. In this article, we propose a new resource-constrained communication synthesis algorithm for optimizing both inter-island connections (IICs) and latency targeting on distributed register-file microarchitecture (DRFM). The experimental results show that tip to 24.7% and 12.7% reduction on IIC and latency can be achieved respectively as compared to the previous work.
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture Considering Inter-Island Delay
(2010)
Huang, Juinn-Dar
;
Chen, Chia-I
;
Hsu, Wan-Ling
;
Lin, Yen-Ting
;
Jou, Jing-Yang
In deep-submicron era, wire delay is becoming the bottleneck while pursuing high system clock speed. Several distributed register (DR) architectures are proposed to cope with this problem by keeping most wires local. In this paper, we propose the distributed register-file microarchitecture with inter-island delay (DRFM-IID). With such delay consideration, synthesis task is inherently more complicated than the one with no inter-island delay concern since uncertain interconnect latency is very likely to make a serious impact on whole system performance. Hence we also develop a performance-driven architectural synthesis framework targeting DRFM-IID, which takes the number of inter-island transfers, transfer criticality and resource utilization into account for better optimization outcomes. The experimental results show that the latency and the number of inter-cluster transfers can be reduced by 26.9% and 37.5% on average; and the latter is a common indicator for power consumption of on-chip communication.
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay
(2012-02-01)
Huang, Juinn-Dar
;
Chen, Chia-I
;
Hsu, Wan-Ling
;
Lin, Yen-Ting
;
Jou, Jing-Yang
In deep-submicron era, wire delay is becoming a bottleneck while pursuing higher system clock speed. Several distributed register (DR) architectures are proposed to cope with this problem by keeping most wires local. In this article, we propose the distributed register-file microarchitecture with inter-island delay (DRFM-IID). Though DRFM-IID is also one of the DR-based architectures, it is considered more practical than the previously proposed DRFM, in terms of delay model. With such delay consideration, the synthesis task is inherently more complicated than the one without inter-island delay concern since uncertain interconnect latency is very likely to seriously impact on the whole system performance. Therefore we also develop a performance-driven architectural synthesis framework targeting DRFM-IID. Several factors for evaluating the quality of results, such as number of inter-island transfers, timing-criticality of transfer, and resource utilization balancing, are adopted as the guidance while performing architectural synthesis for better optimization outcomes. The experimental results show that the latency and the number of inter-cluster transfers can be reduced by 26.9% and 37.5% on average; and the latter is commonly regarded as an indicator for power consumption of on-chip communication.