Browsing by Author "Hsu, Yarsun"

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DeAr: A Framework for Power-efficient and Flexible Embedded Digital Signal Processor Design
(2016)
Lee, Chi-Ming
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Huang, Yong-Jyun
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Liu, Chih-Wei
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Hsu, Yarsun
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電子工程學系及電子研究所
The evolution of wireless communication protocols drives the quest of power-efficient and flexible computing for embedded DSPs, but popular architectures, very-long-instruction word (VLIW) and application-specific instruction set processor (ASIP), serve as opposite extreme cases in regard to power efficiency and flexibility. To this end, we present DeAr: Dual thread Architecture DSP, which manipulates a multi-banked register file that enables simultaneous multi-threading (SMT), and a transport-triggered bus that exploits the data forwarding mechanism in its compact datapath. We also propose a novel scheduling algorithm which leverages the compact hardware to achieve both high throughput and flexible computation. In the experiment of common DSP kernels, DeAr saves 20.3%43.1% and 31.8%-2.2% of power dissipation, 36.1%-31.5% and 28.2%5.7% of area, compared with VLIW and ASIP respectively.
Multi-mode message passing switch networks applied for QC-LDPC decoder
(2008)
Liu, Chih-Hao
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Lin, Chien-Ching
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Chang, Hsie-Chia
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Lee, Chen-Yi
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Hsu, Yarsun
The multi-mode message passing switch networks for multi-standard QC-LDPC decoder are presented. An enhanced self-routing switch network with only one barrel shifter permutation structure and a shifter-based two-way duplicated switch network are proposed to support 19 and 3 different submatrices defined in IEEE 802.16e and IEEE 802.11n. These proposed switch networks can route the decoding message in parallel by different sizes without signal congestion. The enhanced self-routing switch network can switch the messages at different expansion factors with the lowest hardware complexity. Under the condition of a smaller expansion factor, the decoder throughput can be enhanced from the two-way duplicated switch network by increasing the parallelism. In the 130nm CMOS synthesis result, the proposed enhanced self-routing and the two-way duplicated switch network gate counts are 21.9k and 37.4k at 384MHz operation frequency.
MULTI-MODE MULTI-PARALLELISM DATA EXCHANGE METHOD AND DEVICE THEREOF
(2009-06-11)
LIU, Chih-Hao
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Lin, Chien-Ching
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Lee, Chen-Yi
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Chang, Hsie-Chia
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Hsu, Yarsun
A multi-mode multi-parallelism data exchange method and the device thereof are proposed to apply to a check node operator or a bit node operator. The proposed method comprises the steps of: duplicating part or all of an original shift data as a duplicated shift data; combining the original shift data and the duplicated shift data to form a data block; and using a data block as the unit to shift this data block so as to conveniently retrieve shift data from the shifted data block. With a maximum z factor circuit and duplication of part of data, specifications of different shift sizes can be supported. The functions of shifters of several sizes can therefore be accomplished with the minimum complexity.
OPERATING METHOD APPLIED TO LOW DENSITY PARITY CHECK (LDPC) DECODER AND CIRCUIT THEREOF
(2009-02-05)
LIU, Chih-Hao
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Liao, Yen-Chin
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Lee, Chen-Yi
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Chang, Hsie-Chia
;
Hsu, Yarsun
An operating method applied to low density parity check (LDPC) decoders and the circuit thereof are proposed, in which original bit nodes are incorporated into check nodes for simultaneous operation. The bit node messages are generated according to the different between the newly generated check messages and the previously check node messages. The bit node messages can be updated immediately, and the decoder throughput can be improved. In the other way, the required memory of LDPC decoders can be effectively reduced, and the decoding speed can also be enhanced.