Browsing by Author "Hu, Boyu"

Now showing 1 - 8 of 8

A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection
(2017-04-01)
Du, Yuan
;
Cho, Wei-Han
;
Huang, Po-Tsang
;
Li, Yilei
;
Wong, Chien-Heng
A cognitive tri-band transmitter (TX) with a forwarded clock using multiband signaling and high-order digital signal modulations is presented for serial link applications. The TX features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level at the receiver side, and then adapting modulation scheme, data bandwidth, and carrier frequencies accordingly based on detected channel information. The supported modulation scheme ranges from nonreturn to zero/Quadrature phase shift keying (QPSK) to Pulse-amplitude modulation (PAM) 16/256-Quadrature amplitude modulation(QAM). The proposed highly reconfigurable TX is capable of dealing with low-cost serial channels, such as low-cost connectors, cables, or multidrop buses with deep and narrow notches in the frequency domain (e.g., a 40-dB loss at notches). The adaptive multiband scheme mitigates equalization requirements and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth. The implemented TX prototype consumes a 14.7-mW power and occupies 0.016 mm(2) in a 28-nm CMOS. It achieves a maximum data rate of 16 Gb/s with forwarded clock through one differential pair and the most energy efficient figure of merit of 20.4 mu W/Gb/s/dB, which is calculated based on power consumption of transmitting per gigabits per second data and simultaneously overcoming per decibel worst case channel loss within the Nyquist frequency.
A 20Gb/s 79.5mW 127GHz CMOS Transceiver with Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications
(2018-01-01)
Kim, Yanghyo
;
Hu, Boyu
;
Du, Yuan
;
Tang, Adrian
;
Chen, Huan-Neng
A 20Gb/s 79.5mW 127GHz CMOS Transceiver with Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications
(2018-01-01)
Kim, Yanghyo
;
Hu, Boyu
;
Du, Yuan
;
Tang, Adrian
;
Chen, Huan-Neng
A Millimeter-Wave CMOS Transceiver With Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications
(2019-06-01)
Kim, Yanghyo
;
Hu, Boyu
;
Du, Yuan
;
Cho, Wei-Han
;
Huang, Rulin
This paper presents a millimeter-wave (127 GHz) CMOS transceiver with a digital pre-distortion capable PAM-4 modulator for contactless communications. The transmitter upconverts PAM-4 modulated baseband signals through a free-running 127-GHz oscillator and single-balanced mixer, and it delivers PAM-4 modulated carrier signals to a folded-dipole antenna, which is designed on a FR408HR substrate. The receiver's low-noise amplifier provides a 10-dB gain, and the self-mixer downconverts carrier-modulated PAM-4 signals to base-band signals without the necessity of carrier synchronization. The PAM-4 modulator pre-distorts the baseband signals and corrects the non-linear characteristics of the transmitter's upconversion mixer and the receiver's downconversion self-mixer. Designed and fabricated in a 65-nm CMOS process, the demonstrated system transfers 20 Gb/s of PAM-4 modulated data through a 1-mm air gap and consumes 79.5 mW (transmitter: 50.8 mW and receiver: 28.7 mW) of power under a 1.2-V supply, achieving a 3.98-pJ/bit energy efficiency. The communication distance is extended to 3 cm by inserting a dielectric waveguide between the same transceiver.
An 8.8-GS/s 8b Time-Interleaved SAR ADC with 50-dB SFDR Using Complementary Dual-Loop-Assisted Buffers in 28nm CMOS
(2018-01-01)
Wang, X. Shawn
;
Chan, Chi-Hang
;
Du, Jieqiong
;
Wong, Chien-Heng
;
Li, Yilei
This paper presents an 8.8 GS/s 16-way time-interleaved asynchronous SAR ADC fabricated in 28-nm CMOS technology. A two-level 2x8 master-slave hierarchical interleaved architecture is employed. A complementary dual-loop-assisted buffer is proposed to achieve both high linearity and bandwidth with low power. This time-interleaved ADC achieves 38.4-dB SNDR and 50-dB SFDR with a Nyquist input at 8.8 GS/s sampling rate and consumes 83.4 mW, resulting in a 140 fJ/conv.-step Walden FOM with buffers.
An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT)
(2019-10-01)
Du, Yuan
;
Du, Li
;
Gu, Xuefeng
;
Du, Jieqiong
;
Wang, X. Shawn
An analog neural network computing engine based on CMOS-compatible charge-trap transistor (CTT) is proposed in this paper. CTT devices are used as analog multipliers. Compared to digital multipliers, CTT-based analog multiplier shows significant area and power reduction. The proposed computing engine is composed of a scalable CTT multiplier array and energy efficient analog-digital interfaces. By implementing the sequential analog fabric, the engine's mixed-signal interfaces are simplified and hardware overhead remains constant regardless of the size of the array. A proof-of-concept 784 by 784 CTT computing engine is implemented using TSMC 28-nm CMOS technology and occupies 0.68 mm(2). The simulated performance achieves 76.8 TOPS (8-bit) with 500 MHz clock frequency and consumes 14.8 mW. As an example, we utilize this computing engine to address a classic pattern recognition problem-classifying handwritten digits on MNIST database and obtained a performance comparable to state-of-the-art fully connected neural networks using 8-bit fixed-point resolution.
Digital PLL for Phase Noise Cancellation in Ring Oscillator-Based I/Q Receivers
(2016)
Chen, Zuow-Zun
;
Li, Yilei
;
Kuan, Yen-Cheng
;
Hu, Boyu
;
Wong, Chien-Heng
A digital phase noise cancellation technique for ring oscillator-based I/Q receivers is presented. Ring oscillator phase noise, including supply-induced phase noise, is extracted from digital phase-locked loop (DPLL) and used to restore the randomly rotated baseband signal in digital domain. The receiver prototype fabricated in 65nm CMOS technology achieves phase noise reduction from - 88 to - 109dBc/Hz at 1MHz offset, and an integrated phase noise (IPN) reduction from - 16.8 to - 34.6dBc, when operating at 2.4GHz.
DPLL for Phase Noise Cancellation in Ring Oscillator-Based Quadrature Receivers
(2017-04-01)
Chen, Zuow-Zun
;
Kuan, Yen-Cheng
;
Li, Yilei
;
Hu, Boyu
;
Wong, Chien-Heng
In this paper, a low overhead phase noise cancellation technique for ring oscillator (RO)-based quadrature receivers is presented. The proposed technique operates in background and extracts RO phase noise as well as supply-induced phase noise from the digital phase-locked loop. The obtained phase noise information is then used to restore the randomly rotated baseband signal in digital domain. A receiver prototype is fabricated in standard 65-nm CMOS technology. It demonstrates a phase noise reduction from -88 to -109 dBc/Hz at 1-MHz offset and an integrated phase noise reduction from -16.8 to -34.6 dBc when operating at 2.4 GHz.