Browsing by Author "Hu, Chia-Ying"

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Impacts of the Shell Doping Profile on the Electrical Characteristics of Junctionless FETs
(2015-11-01)
Kumar, Malkundi Puttaveerappa Vijay
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Hu, Chia-Ying
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Kao, Kuo-Hsing
;
Lee, Yao-Jen
;
Chao, Tien-Sheng
This paper presents the impacts of an advanced shell doping profile (SDP) on the electrical characteristics of a junctionless (JL) FET in terms of OFF-current, subthreshold swing (SS), and ON-current by a numerical simulator. Due to the potential mirroring effect, a special observation stemming from the SDP, the carriers can enter the intrinsic region from the doped surface reducing the series resistance though the junction depth is smaller than 5 nm. The proposed doping profile provides an additional structure parameter for designing a JL FET showing the mitigated short-channel effects, a better SS, and a higher ON/OFF current ratio for sub-20-nm channel length. Compared with traditional devices, a JL FET with the proposed SDP shows a lower OFF-current by decades and less electrical characteristics variation caused by the nanowire diameter variation. The SDP not only reduces the series resistance of a JL FET but also poses a possible solution of avoiding the negative impacts of quantum confinement for advanced technology nodes.
Improving the Electrical Performance of a Quantum Well FET With a Shell Doping Profile by Heterojunction Optimization
(2017-09-01)
Kumar, Malkundi Puttaveerappa Vijay
;
Hu, Chia-Ying
;
Walke, Amey Mahadev
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Kao, Kuo-Hsing
;
Chao, Tien-Sheng
This paper investigates the impacts of typical semiconductor material properties-electron affinity, bandgap, and dielectric constant, on the electrical performance of a p-type core-shell heterojunction nanowire FET by numerical simulations. At the heterojunction, a valence band offset of 200 meV forms a sufficient energy barrier confining the holes in the quantum well, resulting in the optimal OFF-state current. A higher dielectric constant of the shell region is found to be able to decrease the leakage current of the device. The optimum conditions from the parameter analysis are demonstrated by a realistic and achievable material combination of Si/SiGe for the core-shell configuration. This paper provides physical insights into the materialwise impacts for designing the proposed transistor showing the reduced OFF-current and a better subthreshold swing for low-power applications.