Browsing by Author "Hu, Hsiang-Sheng"

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Novel FFT Processor with Parallel-In-Parallel-Out in Normal Order
(2009)
Hu, Hsiang-Sheng
;
Chen, Hsiao-Yun
;
Jou, Shyh-Jye
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel FFT processor that can provide parallel-in-parallel-out in normal order is proposed for high throughput required OFDM communication system, such as discrete Fourier transform (DFT)-based channel estimation in IEEE 802.16c. The hardware implementation results show the proposed 1024-point FFT architecture can achieve the throughput rate up to 1.28 G samples/sec and the execution time down to 7.3 us when working at 160 MHz. When working at the system required 83.3 MHz, it consumes 21.7 mW with 134474 gates (including memory) that occupy 0.471 mm(2) by using 90 rim, IV CMOS process.
STBC-OFDM Downlink Baseband Receiver for Mobile WMAN
(2013-01-01)
Chen, Hsiao-Yun
;
Lin, Jyun-Nan
;
Hu, Hsiang-Sheng
;
Jou, Shyh-Jye
;
電子工程學系及電子研究所
This paper proposes a space time block code-orthogonal frequency division multiplexing downlink baseband receiver for mobile wireless metropolitan area network. The proposed baseband receiver applied in the system with two transmit antennas and one receive antenna aims to provide high performance in outdoor mobile environments. It provides a simple and robust synchronizer and an accurate but hardware affordable channel estimator to overcome the challenge of multipath fading channels. The coded bit error rate performance for 16 quadrature amplitude modulation can achieve less than 10(-6) under the vehicle speed of 120 km/hr. The proposed baseband receiver designed in 90-nm CMOS technology can support up to 27.32 Mb/s uncoded data transmission under 10 MHz channel bandwidth. It requires a core area of 2.41 x 2.41 mm(2) and dissipates 68.48 mW at 78.4 MHz with 1 V power supply.